Volume 3A System Programming Guide_ Part 1 (794103), страница 37
Текст из файла (страница 37)
This causes theprocessor to store an aligned word, followed by an aligned doubleword. User-modeprograms normally do not store pseudo-descriptors, but the possibility of generatingan alignment check fault can be avoided by aligning pseudo-descriptors in this way.The same alignment should be used when storing the IDTR register using the SIDTinstruction.
When storing the LDTR or task register (using the SLTR or STR instruction, respectively), the pseudo-descriptor should be located at a doubleword address(that is, address MOD 4 is equal to 0).Vol. 3 3-21PROTECTED-MODE MEMORY MANAGEMENT4716 15790Limit32-bit Base Address16 1564-bit Base Address0LimitFigure 3-11. Pseudo-Descriptor Formats3.5.2Segment Descriptor Tables in IA-32e ModeIn IA-32e mode, a segment descriptor table can contain up to 8192 (213) 8-bytedescriptors. An entry in the segment descriptor table can be 8 bytes.
System descriptors are expanded to 16 bytes (occupying the space of two entries).GDTR and LDTR registers are expanded to hold 64-bit base address. The corresponding pseudo-descriptor is 80 bits. (see the bottom diagram in Figure 3-11).The following system descriptors expand to 16 bytes:— Call gate descriptors (see Section 4.8.3.1, “IA-32e Mode Call Gates”)— IDT gate descriptors (see Section 5.14.1, “64-Bit Mode IDT”)— LDT and TSS descriptors (see Section 6.2.3, “TSS Descriptor in 64-bitmode”).3.6PAGING (VIRTUAL MEMORY) OVERVIEWWhen operating in protected mode, IA-32 architecture permits linear address spaceto be mapped directly into a large physical memory (for example, 4 GBytes of RAM)or indirectly (using paging) into a smaller physical memory and disk storage. Thislatter method of mapping the linear address space is referred to as virtual memory ordemand-paged virtual memory.When paging is used, the processor divides the linear address space into fixed-sizepages (of 4 KBytes, 2 MBytes, or 4 MBytes in length) that can be mapped into physical memory and/or disk storage.
When a program (or task) references a logicaladdress in memory, the processor translates the address into a linear address andthen uses its paging mechanism to translate the linear address into a correspondingphysical address.If the page containing the linear address is not currently in physical memory, theprocessor generates a page-fault exception (#PF). The exception handler for thepage-fault exception typically directs the operating system or executive to load thepage from disk storage into physical memory (perhaps writing a different page fromphysical memory out to disk in the process). When the page has been loaded in physical memory, a return from the exception handler causes the instruction that gener-3-22 Vol.
3PROTECTED-MODE MEMORY MANAGEMENTated the exception to be restarted. The information that the processor uses to maplinear addresses into the physical address space and to generate page-fault exceptions (when necessary) is contained in page directories and page tables stored inmemory.Paging is different from segmentation through its use of fixed-size pages. Unlikesegments, which usually are the same size as the code or data structures they hold,pages have a fixed size. If segmentation is the only form of address translation used,a data structure present in physical memory will have all of its parts in memory. Ifpaging is used, a data structure can be partly in memory and partly in disk storage.To minimize the number of bus cycles required for address translation, the mostrecently accessed page-directory and page-table entries are cached in the processorin devices called translation lookaside buffers (TLBs).
The TLBs satisfy most requestsfor reading the current page directory and page tables without requiring a bus cycle.Extra bus cycles occur only when the TLBs do not contain a page-table entry, whichtypically happens when a page has not been accessed for a long time. See Section3.12, “Translation Lookaside Buffers (TLBs)”, for more information on the TLBs.3.6.1Paging OptionsPaging is controlled by three flags in the processor’s control registers:•PG (paging) flag. Bit 31 of CR0 (available in all IA-32 processors beginning withthe Intel386 processor).•PSE (page size extensions) flag.
Bit 4 of CR4 (introduced in the Pentiumprocessor).•PAE (physical address extension) flag. Bit 5 of CR4 (introduced in thePentium Pro processors).The PG flag enables the page-translation mechanism. The operating system or executive usually sets this flag during processor initialization. The PG flag must be set ifthe processor’s page-translation mechanism is to be used to implement a demandpaged virtual memory system or if the operating system is designed to run morethan one program (or task) in virtual-8086 mode.The PSE flag enables large page sizes: 4-MByte pages or 2-MByte pages (when thePAE flag is set). When the PSE flag is clear, the more common page length of4 KBytes is used. See Section 3.7.2, “Linear Address Translation (4-MByte Pages)”,Section 3.8.3, “Linear Address Translation With PAE Enabled (2-MByte Pages)”, andSection 3.9, “36-Bit Physical Addressing Using the PSE-36 Paging Mechanism” formore information about the use of the PSE flag.The PAE flag provides a method of extending physical addresses to 36 bits.
Thisphysical address extension can only be used when paging is enabled. It relies on anadditional page directory pointer table that is used along with page directories andpage tables to reference physical addresses above FFFFFFFFH. See Section 3.8, “36Bit Physical Addressing Using the PAE Paging Mechanism”, for more informationabout extending physical addresses using the PAE flag.Vol. 3 3-23PROTECTED-MODE MEMORY MANAGEMENTWhen PAE flag is enabled for Intel 64 processors, the PAE mechanism is enhanced tosupport more than 36 bits of physical addressing (if the processor’s implementationsupports more than 36 bits of physical addressing). This applies to IA-32e modeaddress translation (see Section 3.10, “PAE-Enabled Paging in IA-32e Mode”) andenhanced legacy PAE-enabled address translation (see Section 3.8.1, “EnhancedLegacy PAE Paging”).The 36-bit page size extension (PSE-36) feature provides an alternate method ofextending physical addressing to 36 bits.
This paging mechanism uses the page sizeextension mode (enabled with the PSE flag) and modified page directory entries toreference physical addresses above FFFFFFFFH. The PSE-36 feature flag (bit 17 in theEDX register when the CPUID instruction is executed with a source operand of 1)indicates the availability of this addressing mechanism. See Section 3.9, “36-BitPhysical Addressing Using the PSE-36 Paging Mechanism”, for more informationabout the PSE-36 physical address extension and page size extension mechanism.3.6.2Page Tables and Directories in the Absence of Intel® 64TechnologyThe information that the processor uses to translate linear addresses into physicaladdresses (when paging is enabled) is contained in four data structures:•Page directory — An array of 32-bit page-directory entries (PDEs) contained ina 4-KByte page.
Up to 1024 page-directory entries can be held in a pagedirectory.•Page table — An array of 32-bit page-table entries (PTEs) contained in a4-KByte page. Up to 1024 page-table entries can be held in a page table. (Pagetables are not used for 2-MByte or 4-MByte pages. These page sizes are mappeddirectly from one or more page-directory entries.)••Page — A 4-KByte, 2-MByte, or 4-MByte flat address space.Page-Directory-Pointer Table — An array of four 64-bit entries, each of whichpoints to a page directory. This data structure is only used when the physicaladdress extension is enabled (see Section 3.8, “36-Bit Physical Addressing Usingthe PAE Paging Mechanism”).These tables provide access to either 4-KByte or 4-MByte pages when normal 32-bitphysical addressing is being used and to either 4-KByte or 2-MByte pages or 4-MBytepages only when extended (36-bit) physical addressing is being used.Table 3-3 shows the page size and physical address size obtained from varioussettings of the paging control flags and the PSE-36 CPUID feature flag.
Each pagedirectory entry contains a PS (page size) flag that specifies whether the entry pointsto a page table whose entries in turn point to 4-KByte pages (PS set to 0) or whetherthe page-directory entry points directly to a 4-MByte (PSE and PS set to 1) or2-MByte page (PAE and PS set to 1).3-24 Vol. 3PROTECTED-MODE MEMORY MANAGEMENT3.7PAGE TRANSLATION USING 32-BIT PHYSICALADDRESSINGThe following sections describe the IA-32 architecture’s page translation mechanismwhen using 32-bit physical addresses and a maximum physical address space of4 GBytes. The 32-bit physical addressing described applies to IA-32 processors orwhen the following situations are all true:••The processor supports Intel 64 architecture but IA-32e mode is not active.PAE or PSE mechanism is not active.Section 3.8, “36-Bit Physical Addressing Using the PAE Paging Mechanism” andSection 3.9, “36-Bit Physical Addressing Using the PSE-36 Paging Mechanism”describe extensions to this page translation mechanism to support 36-bit physicaladdresses and a maximum physical address space of 64 GBytes.Table 3-3.
Page Sizes and Physical Address SizesPG Flag,CR0PAE Flag,CR4PSE Flag,CR40XXX100X1010101110111X11X3.7.1PS Flag,PDEPSE-36 CPUIDFeature FlagPage SizePhysical AddressSizeX—Paging DisabledX4 KBytes32 BitsX4 KBytes32 Bits04 MBytes32 Bits114 MBytes36 Bits0X4 KBytes36 Bits1X2 MBytes36 BitsLinear Address Translation (4-KByte Pages)Figure 3-12 shows the page directory and page-table hierarchy when mapping linearaddresses to 4-KByte pages. The entries in the page directory point to page tables,and the entries in a page table point to pages in physical memory. This pagingmethod can be used to address up to 220 pages, which spans a linear address spaceof 232 bytes (4 GBytes).Vol.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
