Volume 3A System Programming Guide_ Part 1 (794103), страница 38
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3 3-25PROTECTED-MODE MEMORY MANAGEMENTLinear Address3122 2112 11TableDirectory0Offset121010Page Table4-KByte PagePhysical AddressPage DirectoryPage-Table Entry20Directory Entry1024 PDE ∗ 1024 PTE = 220 Pages32*CR3 (PDBR)*32 bits aligned onto a 4-KByte boundary.Figure 3-12. Linear Address Translation (4-KByte Pages)To select the various table entries, the linear address is divided into three sections:•Page-directory entry — Bits 22 through 31 provide an offset to an entry in thepage directory.
The selected entry provides the base physical address of a pagetable.•Page-table entry — Bits 12 through 21 of the linear address provide an offset toan entry in the selected page table. This entry provides the base physical addressof a page in physical memory.•Page offset — Bits 0 through 11 provides an offset to a physical address in thepage.Memory management software has the option of using one page directory for allprograms and tasks, one page directory for each task, or some combination of thetwo.3.7.2Linear Address Translation (4-MByte Pages)Figure 3-13 shows how a page directory can be used to map linear addresses to4-MByte pages.
The entries in the page directory point to 4-MByte pages in physicalmemory. This paging method can be used to map up to 1024 pages into a 4-GBytelinear address space.3-26 Vol. 3PROTECTED-MODE MEMORY MANAGEMENT31Linear Address22 21OffsetDirectory2210Page DirectoryDirectory Entry32*04-MByte PagePhysical Address101024 PDE = 1024 PagesCR3 (PDBR)*32 bits aligned onto a 4-KByte boundary.Figure 3-13. Linear Address Translation (4-MByte Pages)The 4-MByte page size is selected by setting the PSE flag in control register CR4 andsetting the page size (PS) flag in a page-directory entry (see Figure 3-14). Withthese flags set, the linear address is divided into two sections:•Page directory entry—Bits 22 through 31 provide an offset to an entry in the pagedirectory.
The selected entry provides the base physical address of a 4-MBytepage.•Page offset—Bits 0 through 21 provides an offset to a physical address in thepage.NOTE(For the Pentium processor only.) When enabling or disabling largepage sizes, the TLBs must be invalidated (flushed) after the PSE flagin control register CR4 has been set or cleared. Otherwise, incorrectpage translation might occur due to the processor using outdatedpage translation information stored in the TLBs.
See Section 10.9,“Invalidating the Translation Lookaside Buffers (TLBs)”, forinformation on how to invalidate the TLBs.3.7.3Mixing 4-KByte and 4-MByte PagesWhen the PSE flag in CR4 is set, both 4-MByte pages and page tables for 4-KBytepages can be accessed from the same page directory. If the PSE flag is clear, onlypage tables for 4-KByte pages can be accessed (regardless of the setting of the PSflag in a page-directory entry).Vol. 3 3-27PROTECTED-MODE MEMORY MANAGEMENTA typical example of mixing 4-KByte and 4-MByte pages is to place the operatingsystem or executive’s kernel in a large page to reduce TLB misses and thus improveoverall system performance.The processor maintains 4-MByte page entries and 4-KByte page entries in separateTLBs.
So, placing often used code such as the kernel in a large page, frees up4-KByte-page TLB entries for application programs and tasks.3.7.4Memory AliasingThe IA-32 architecture permits memory aliasing by allowing two page-directoryentries to point to a common page-table entry. Software that needs to implementmemory aliasing in this manner must manage the consistency of the accessed anddirty bits in the page-directory and page-table entries. Allowing the accessed anddirty bits for the two page-directory entries to become inconsistent may lead to aprocessor deadlock.3.7.5Base Address of the Page DirectoryThe physical address of the current page directory is stored in the CR3 register (alsocalled the page directory base register or PDBR).
(See Figure 2-6 and Section 2.5,“Control Registers”, for more information on the PDBR.) If paging is to be used, thePDBR must be loaded as part of the processor initialization process (prior to enablingpaging). The PDBR can then be changed either explicitly by loading a new value inCR3 with a MOV instruction or implicitly as part of a task switch.
(See Section 6.2.1,“Task-State Segment (TSS)”, for a description of how the contents of the CR3register is set for a task.)There is no present flag in the PDBR for the page directory. The page directory maybe not-present (paged out of physical memory) while its associated task issuspended, but the operating system must ensure that the page directory indicatedby the PDBR image in a task's TSS is present in physical memory before the task isdispatched. The page directory must also remain in memory as long as the task isactive.3.7.6Page-Directory and Page-Table EntriesFigure 3-14 shows the format for the page-directory and page-table entries when4-KByte pages and 32-bit physical addresses are being used.
Figure 3-15 showsthe format for the page-directory entries when 4-MByte pages and 32-bit physicaladdresses are being used. The functions of the flags and fields in the entries inFigures 3-14 and 3-15 are as follows:Page base address, bits 12 through 32(Page-table entries for 4-KByte pages) — Specifies the physicaladdress of the first byte of a 4-KByte page. The bits in this field are3-28 Vol. 3PROTECTED-MODE MEMORY MANAGEMENTinterpreted as the 20 most-significant bits of the physical address,which forces pages to be aligned on 4-KByte boundaries.Page-Directory Entry (4-KByte Page Table)3112 11Page-Table Base Address9 8 7 6 5 4 3 2 1 0AvailP P U RG P 0 A C W / / PSD T S WAvailable for system programmer’s useGlobal page (Ignored)Page size (0 indicates 4 KBytes)Reserved (set to 0)AccessedCache disabledWrite-throughUser/SupervisorRead/WritePresentPage-Table Entry (4-KByte Page)3112 11Page Base AddressAvail9 8 7 6 5 4 3 2 1 0PP P U RG A D A C W / / PTD T S WAvailable for system programmer’s useGlobal PagePage Table Attribute IndexDirtyAccessedCache DisabledWrite-ThroughUser/SupervisorRead/WritePresentFigure 3-14.
Format of Page-Directory and Page-Table Entries for 4-KByte Pagesand 32-Bit Physical Addresses(Page-directory entries for 4-KByte page tables) — Specifies thephysical address of the first byte of a page table. The bits in this fieldare interpreted as the 20 most-significant bits of the physical address,which forces page tables to be aligned on 4-KByte boundaries.(Page-directory entries for 4-MByte pages) — Specifies the physicaladdress of the first byte of a 4-MByte page.
Only bits 22 through 31 ofthis field are used (and bits 12 through 21 are reserved and must beset to 0, for IA-32 processors through the Pentium II processor). TheVol. 3 3-29PROTECTED-MODE MEMORY MANAGEMENTbase address bits are interpreted as the 10 most-significant bits of thephysical address, which forces 4-MByte pages to be aligned on4-MByte boundaries.Page-Directory Entry (4-MByte Page)3113 12 1122 21Page Base AddressReservedPAT9 8 7 6 5 4 3 2 1 0P P U RAvail. G P D A C W / / PSD T S WPage Table Attribute IndexAvailable for system programmer’s useGlobal pagePage size (1 indicates 4 MBytes)DirtyAccessedCache disabledWrite-throughUser/SupervisorRead/WritePresentFigure 3-15. Format of Page-Directory Entries for 4-MByte Pages and 32-BitAddressesPresent (P) flag, bit 0Indicates whether the page or page table being pointed to by theentry is currently loaded in physical memory. When the flag is set, thepage is in physical memory and address translation is carried out.When the flag is clear, the page is not in memory and, if the processorattempts to access the page, it generates a page-fault exception(#PF).The processor does not set or clear this flag; it is up to the operatingsystem or executive to maintain the state of the flag.If the processor generates a page-fault exception, the operatingsystem generally needs to carry out the following operations:1.
Copy the page from disk storage into physical memory.2. Load the page address into the page-table or page-directoryentry and set its present flag. Other flags, such as the dirty andaccessed flags, may also be set at this time.3. Invalidate the current page-table entry in the TLB (see Section3.12, “Translation Lookaside Buffers (TLBs)”, for a discussion ofTLBs and how to invalidate them).4. Return from the page-fault handler to restart the interruptedprogram (or task).3-30 Vol. 3PROTECTED-MODE MEMORY MANAGEMENTRead/write (R/W) flag, bit 1Specifies the read-write privileges for a page or group of pages (in thecase of a page-directory entry that points to a page table).
When thisflag is clear, the page is read only; when the flag is set, the page canbe read and written into. This flag interacts with the U/S flag and theWP flag in register CR0. See Section 4.11, “Page-Level Protection”,and Table 4-3 for a detailed discussion of the use of these flags.User/supervisor (U/S) flag, bit 2Specifies the user-supervisor privileges for a page or group of pages(in the case of a page-directory entry that points to a page table).When this flag is clear, the page is assigned the supervisor privilegelevel; when the flag is set, the page is assigned the user privilegelevel. This flag interacts with the R/W flag and the WP flag in registerCR0. See Section 4.11, “Page-Level Protection”, and Table 4-3 for adetail discussion of the use of these flags.Page-level write-through (PWT) flag, bit 3Controls the write-through or write-back caching policy of individualpages or page tables.
When the PWT flag is set, write-through cachingis enabled for the associated page or page table; when the flag isclear, write-back caching is enabled for the associated page or pagetable. The processor ignores this flag if the CD (cache disable) flag inCR0 is set. See Section 10.5, “Cache Control”, for more informationabout the use of this flag. See Section 2.5, “Control Registers”, for adescription of a companion PWT flag in control register CR3.Page-level cache disable (PCD) flag, bit 4Controls the caching of individual pages or page tables.
When the PCDflag is set, caching of the associated page or page table is prevented;when the flag is clear, the page or page table can be cached. This flagpermits caching to be disabled for pages that contain memorymapped I/O ports or that do not provide a performance benefit whencached. The processor ignores this flag (assumes it is set) if the CD(cache disable) flag in CR0 is set. See Chapter 10, “Memory CacheControl”, for more information about the use of this flag. See Section2.5, “Control Registers”, for a description of a companion PCD flag incontrol register CR3.Accessed (A) flag, bit 5Indicates whether a page or page table has been accessed (read fromor written to) when set.
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