Volume 3A System Programming Guide_ Part 1 (794103), страница 39
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Memory management software typicallyclears this flag when a page or page table is initially loaded into physical memory. The processor then sets this flag the first time a page orpage table is accessed.This flag is a “sticky” flag, meaning that once set, the processor doesnot implicitly clear it. Only software can clear this flag. The accessedand dirty flags are provided for use by memory management softwareVol.
3 3-31PROTECTED-MODE MEMORY MANAGEMENTto manage the transfer of pages and page tables into and out of physical memory.NOTE: The accesses used by the processor to set this bit may or maynot be exposed to the processor’s Self-Modifying Code detection logic.If the processor is executing code from the same memory area that isbeing used for page table structures, the setting of the bit may or maynot result in an immediate change to the executing code stream.Dirty (D) flag, bit 6Indicates whether a page has been written to when set. (This flag isnot used in page-directory entries that point to page tables.) Memorymanagement software typically clears this flag when a page is initiallyloaded into physical memory.
The processor then sets this flag thefirst time a page is accessed for a write operation.This flag is “sticky,” meaning that once set, the processor does notimplicitly clear it. Only software can clear this flag. The dirty andaccessed flags are provided for use by memory management softwareto manage the transfer of pages and page tables into and out of physical memory.NOTE: The accesses used by the processor to set this bit may or maynot be exposed to the processor’s Self-Modifying Code detection logic.If the processor is executing code from the same memory area that isbeing used for page table structures, the setting of the bit may or maynot result in an immediate change to the executing code stream.Page size (PS) flag, bit 7 page-directory entries for 4-KByte pagesDetermines the page size.
When this flag is clear, the page size is 4KBytes and the page-directory entry points to a page table. When theflag is set, the page size is 4 MBytes for normal 32-bit addressing (and2 MBytes if extended physical addressing is enabled) and the pagedirectory entry points to a page. If the page-directory entry points toa page table, all the pages associated with that page table will be4-KByte pages.Page attribute table index (PAT) flag, bit 7 in page-table entries for 4-KBytepages and bit 12 in page-directory entries for 4-MByte pages(Introduced in the Pentium III processor) — Selects PAT entry. Forprocessors that support the page attribute table (PAT), this flag isused along with the PCD and PWT flags to select an entry in the PAT,which in turn selects the memory type for the page (see Section10.12, “Page Attribute Table (PAT)”).
For processors that do notsupport the PAT, this bit is reserved and should be set to 0.Global (G) flag, bit 8(Introduced in the Pentium Pro processor) — Indicates a global pagewhen set. When a page is marked global and the page global enable(PGE) flag in register CR4 is set, the page-table or page-directoryentry for the page is not invalidated in the TLB when register CR3 is3-32 Vol. 3PROTECTED-MODE MEMORY MANAGEMENTloaded or a task switch occurs. This flag is provided to preventfrequently used pages (such as pages that contain kernel or otheroperating system or executive code) from being flushed from theTLB.
Only software can set or clear this flag. For page-directoryentries that point to page tables, this flag is ignored and the globalcharacteristics of a page are set in the page-table entries. SeeSection 3.12, “Translation Lookaside Buffers (TLBs)”, for more information about the use of this flag. (This bit is reserved in Pentium andearlier IA-32 processors.)Reserved and available-to-software bitsFor all IA-32 processors.
Bits 9, 10, and 11 are available for use bysoftware. (When the present bit is clear, bits 1 through 31 are available to software, see Figure 3-16.) In a page-directory entry thatpoints to a page table, bit 6 is reserved and should be set to 0. Whenthe PSE and PAE flags in control register CR4 are set, the processorgenerates a page fault if reserved bits are not set to 0.For Pentium II and earlier processors. Bit 7 in a page-table entry isreserved and should be set to 0.
For a page-directory entry for a4-MByte page, bits 12 through 21 are reserved and must be set to 0.For Pentium III and later processors. For a page-directory entry for a4-MByte page, bits 13 through 21 are reserved and must be set to 0.3.7.7Not Present Page-Directory and Page-Table EntriesWhen the present flag is clear for a page-table or page-directory entry, the operatingsystem or executive may use the rest of the entry for storage of information such asthe location of the page in the disk storage system (see Figure 3-16).310Available to Operating System or Executive0Figure 3-16.
Format of a Page-Table or Page-Directory Entry for a Not-Present Page3.836-BIT PHYSICAL ADDRESSING USING THE PAEPAGING MECHANISMThe PAE paging mechanism and support for 36-bit physical addressing were introduced into the IA-32 architecture in the Pentium Pro processors. Implementation ofthis feature in an IA-32 processor is indicated with CPUID feature flag PAE (bit 6 inthe EDX register when the source operand for the CPUID instruction is 2). The physical address extension (PAE) flag in register CR4 enables the PAE mechanism andextends physical addresses from 32 bits to 36 bits.
Here, the processor provides 4Vol. 3 3-33PROTECTED-MODE MEMORY MANAGEMENTadditional address line pins to accommodate the additional address bits. To use thisoption, the following flags must be set:••PG flag (bit 31) in control register CR0—Enables pagingPAE flag (bit 5) in control register CR4 are set—Enables the PAE pagingmechanism.When the PAE paging mechanism is enabled, the processor supports two sizes ofpages: 4-KByte and 2-MByte. As with 32-bit addressing, both page sizes can beaddressed within the same set of paging tables (that is, a page-directory entry canpoint to either a 2-MByte page or a page table that in turn points to 4-KByte pages).To support the 36-bit physical addresses, the following changes are made to thepaging data structures:•The paging table entries are increased to 64 bits to accommodate 36-bit basephysical addresses.
Each 4-KByte page directory and page table can thus haveup to 512 entries.•A new table, called the page-directory-pointer table, is added to the linearaddress translation hierarchy. This table has 4 entries of 64-bits each, and it liesabove the page directory in the hierarchy. With the physical address extensionmechanism enabled, the processor supports up to 4 page directories.•The 20-bit page-directory base address field in register CR3 (PDBR) is replacedwith a 27-bit page-directory-pointer-table base address field. The updated fieldprovides the 27 most-significant bits of the physical address of the first byte ofthe page-directory pointer table (forcing the table to be located on a 32-byteboundary).Since CR3 now contains the page-directory-pointer-table base address, it can bereferred to as the page-directory-pointer-table register (PDPTR).
SeeFigure 3-17.•Linear address translation is changed to allow mapping 32-bit linear addressesinto the larger physical address space.310Page-Directory-Pointer-Table Base AddressP PC W 0 0 0D TFigure 3-17. Register CR3 Format When the Physical Address Extension is Enabled3.8.1Enhanced Legacy PAE PagingOn Intel 64 processors, the page directory pointer entry supports physical addresssize of the underlying implementation (reported by CPUID.80000008H).
Legacy PAEenabled paging [see Section 3.8.2, “Linear Address Translation With PAE Enabled(4-KByte Pages)” and Section 3.8.3, “Linear Address Translation With PAE Enabled(2-MByte Pages)”] can address physical memory greater than 64-GByte if theimplementation’s physical address size is greater than 36 bits.3-34 Vol. 3PROTECTED-MODE MEMORY MANAGEMENT3.8.2Linear Address Translation With PAE Enabled (4-KBytePages)Figure 3-18 shows the page-directory-pointer, page-directory, and page-table hierarchy when mapping linear addresses to 4-KByte pages when the PAE paging mechanism enabled.
This paging method can be used to address up to 220 pages, whichspans a linear address space of 232 bytes (4 GBytes).To select the various table entries, the linear address is divided into three sections:•Page-directory-pointer-table entry—Bits 30 and 31 provide an offset to one of the4 entries in the page-directory-pointer table.
The selected entry provides thebase physical address of a page directory.•Page-directory entry—Bits 21 through 29 provide an offset to an entry in theselected page directory. The selected entry provides the base physical address ofa page table.•Page-table entry—Bits 12 through 20 provide an offset to an entry in the selectedpage table. This entry provides the base physical address of a page in physicalmemory.•Page offset—Bits 0 through 11 provide an offset to a physical address in thepage.Directory PointerLinear Address31 30 2921 2012 11TableDirectory0Offset12Page TablePage Directory4-KByte PagePhysical Address9Page-Table Entry924Directory Entry2Page-DirectoryPointer TableDir.
Pointer Entry32*4 PDPTE ∗ 512 PDE ∗ 512 PTE = 220 PagesCR3 (PDPTR)*32 bits aligned onto a 32-byte boundaryFigure 3-18. Linear Address Translation With PAE Enabled (4-KByte Pages)Vol. 3 3-35PROTECTED-MODE MEMORY MANAGEMENT3.8.3Linear Address Translation With PAE Enabled (2-MBytePages)Figure 3-19 shows how a page-directory-pointer table and page directories can beused to map linear addresses to 2-MByte pages when the PAE paging mechanismenabled. This paging method can be used to map up to 2048 pages (4 page-directory-pointer-table entries times 512 page-directory entries) into a 4-GByte linearaddress space.When PAE is enabled, the 2-MByte page size is selected by setting the page size (PS)flag in a page-directory entry (see Figure 3-14).
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