Volume 3A System Programming Guide_ Part 1 (794103), страница 40
Текст из файла (страница 40)
(As shown in Table 3-3, the PSE flagin control register CR4 has no affect on the page size when PAE is enabled.) With thePS flag set, the linear address is divided into three sections:•Page-directory-pointer-table entry—Bits 30 and 31 provide an offset to an entryin the page-directory-pointer table. The selected entry provides the base physicaladdress of a page directory.•Page-directory entry—Bits 21 through 29 provide an offset to an entry in thepage directory. The selected entry provides the base physical address of a2-MByte page.•Page offset—Bits 0 through 20 provides an offset to a physical address in thepage.DirectoryPointerLinear Address31 30 2921 20OffsetDirectory0219Page Directory2-MByte PagePhysical AddressPage-DirectoryPointer Table2Directory Entry15Dir. Pointer Entry4 PDPTE ∗ 512 PDE = 2048 Pages32*CR3 (PDPTR)*32 bits aligned onto a 32-byte boundaryFigure 3-19. Linear Address Translation With PAE Enabled (2-MByte Pages)3-36 Vol.
3PROTECTED-MODE MEMORY MANAGEMENT3.8.4Accessing the Full Extended Physical Address Space Withthe Extended Page-Table StructureThe page-table structure described in the previous two sections allows up to4 GBytes of the 64 GByte extended physical address space to be addressed at onetime.
Additional 4-GByte sections of physical memory can be addressed in either oftwo way:•Change the pointer in register CR3 to point to another page-directory-pointertable, which in turn points to another set of page directories and page tables.•Change entries in the page-directory-pointer table to point to other page directories, which in turn point to other sets of page tables.3.8.5Page-Directory and Page-Table Entries With ExtendedAddressing EnabledFigure 3-20 shows the format for the page-directory-pointer-table, page-directory, and page-table entries when 4-KByte pages and 36-bit extended physicaladdresses are being used. Figure 3-21 shows the format for the page-directorypointer-table and page-directory entries when 2-MByte pages and 36-bit extendedphysical addresses are being used.
The functions of the flags in these entries are thesame as described in Section 3.7.6, “Page-Directory and Page-Table Entries”. Themajor differences in these entries are as follows:••••A page-directory-pointer-table entry is added.The size of the entries are increased from 32 bits to 64 bits.The maximum number of entries in a page directory or page table is 512.The base physical address field in each entry is extended to 24 bits.NOTEOlder IA-32 processors that implement the PAE mechanism useuncached accesses when loading page-directory-pointer tableentries. This behavior is model specific and not architectural. Morerecent Intel 64 and IA-32 processors may cache page-directorypointer table entries.Vol.
3 3-37PROTECTED-MODE MEMORY MANAGEMENTPage-Directory-Pointer-Table Entry6336 35Reserved (set to 0)3112 11Page-Directory Base Address32BaseAddr.9 85 4 3 2 1 0P PReserved C W Res. PD TAvailPage-Directory Entry (4-KByte Page Table)6336 35Reserved (set to 0)3112 11Page-Table Base Address32BaseAddr.9 8 7 6 5 4 3 2 1 0AvailP P U R0 0 0 A C W / / PD T S WPage-Table Entry (4-KByte Page)6336 353112 119 8 7 6 5 4 3 2 1 0PPage Base Address32BaseAddr.Reserved (set to 0)P P U RAvail G A D A C W / / PTD T S WFigure 3-20. Format of Page-Directory-Pointer-Table, Page-Directory, and PageTable Entries for 4-KByte Pages with PAE Enabled3-38 Vol. 3PROTECTED-MODE MEMORY MANAGEMENTPage-Directory-Pointer-Table Entry6336 35Reserved (set to 0)3132BaseAddr.12 11Page Directory Base Address9 8Avail.5 4 3 2 1 0P PReserved C W Res.
PD TPage-Directory Entry (2-MByte Page)6336 35Reserved (set to 0)3121 20Page Base Address13 12 11Reserved (set to 0)32BaseAddr.PAT9 8 7 6 5 4 3 2 1 0P P U RAvail. G 1 D A C W / / PD T S WFigure 3-21. Format of Page-Directory-Pointer-Table and Page-DirectoryEntries for 2-MByte Pages with PAE EnabledThe base physical address in an entry specifies the following, depending on the typeof entry:•Page-directory-pointer-table entry — the physical address of the first byte ofa 4-KByte page directory.•Page-directory entry — the physical address of the first byte of a 4-KByte pagetable or a 2-MByte page.•Page-table entry — the physical address of the first byte of a 4-KByte page.For all table entries (except for page-directory entries that point to 2-MByte pages),the bits in the page base address are interpreted as the 24 most-significant bits of a36-bit physical address, which forces page tables and pages to be aligned on 4-KByteboundaries.
When a page-directory entry points to a 2-MByte page, the base addressis interpreted as the 15 most-significant bits of a 36-bit physical address, whichforces pages to be aligned on 2-MByte boundaries.The present flag (bit 0) in the page-directory-pointer-table entries can be set to 0or 1.
If the present flag is clear, the remaining bits in the page-directory-pointertable entry are available to the operating system. If the present flag is set, the fieldsof the page-directory-pointer-table entry are defined in Figures 3-20 for 4-KBytepages and Figures 3-21 for 2-MByte pages.The page size (PS) flag (bit 7) in a page-directory entry determines if the entry pointsto a page table or a 2-MByte page. When this flag is clear, the entry points to a pagetable; when the flag is set, the entry points to a 2-MByte page.
This flag allows4-KByte and 2-MByte pages to be mixed within one set of paging tables.Vol. 3 3-39PROTECTED-MODE MEMORY MANAGEMENTAccess (A) and dirty (D) flags (bits 5 and 6) are provided for table entries that pointto pages.Bits 9, 10, and 11 in all the table entries for the physical address extension are available for use by software. (When the present flag is clear, bits 1 through 63 are available to software.) All bits in Figure 3-14 that are marked reserved or 0 should be setto 0 by software and not accessed by software.
When the PSE and/or PAE flags incontrol register CR4 are set, the processor generates a page fault (#PF) if reservedbits in page-directory and page-table entries are not set to 0, and it generates ageneral-protection exception (#GP) if reserved bits in a page-directory-pointer-tableentry are not set to 0.3.936-BIT PHYSICAL ADDRESSING USING THE PSE-36PAGING MECHANISMThe PSE-36 paging mechanism provides an alternate method (from the PAE mechanism) of extending physical memory addressing to 36 bits.
This mechanism uses thepage size extension (PSE) mode and a modified page-directory table to map 4-MBytepages into a 64-GByte physical address space. As with the PAE mechanism, theprocessor provides 4 additional address line pins to accommodate the additionaladdress bits.The PSE-36 mechanism was introduced into the IA-32 architecture with the PentiumIII processors. The availability of this feature is indicated with the PSE-36 feature bit(bit 17 of the EDX register when the CPUID instruction is executed with a sourceoperand of 1).As is shown in Table 3-3, the following flags must be set or cleared to enable the PSE36 paging mechanism:•PSE-36 CPUID feature flag — When set, it indicates the availability of the PSE36 paging mechanism on the IA-32 processor on which the CPUID instruction isexecuted.••PG flag (bit 31) in register CR0 — Set to 1 to enable paging.•PSE flag (bit 4) in control register CR4 and the PS flag in PDE — Set to 1 toenable the page size extension for 4-MByte pages.•Or the PSE flag (bit 4) in control register CR4 — Set to 1 and the PS flag (bit7) in PDE— Set to 0 to enable 4-KByte pages with 32-bit addressing (below4 GBytes).PAE flag (bit 5) in control register CR4 — Clear to 0 to disable the PAE pagingmechanism.3-40 Vol.
3PROTECTED-MODE MEMORY MANAGEMENTFigure 3-22 shows how the expanded page directory entry can be used to map a32-bit linear address to a 36-bit physical address. Here, the linear address is dividedinto two sections:•Page directory entry — Bits 22 through 35 provide an offset to an entry in thepage directory. The selected entry provides the 14 most significant bits of a36-bit address, which locates the base physical address of a 4-MByte page.•Page offset — Bits 0 through 21 provides an offset to a physical address in thepage.This paging method can be used to map up to 1024 pages into a 64-GByte physicaladdress space.31Linear Address22 21OffsetDirectory2210Page DirectoryDirectory Entry32*04-MByte PagePhysical Address141024 PDE = 1024 PagesCR3 (PDBR)*32 bits aligned onto a 4-KByte boundary.Figure 3-22.
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