Volume 3A System Programming Guide_ Part 1 (794103), страница 41
Текст из файла (страница 41)
Linear Address Translation (4-MByte Pages)Figure 3-23 shows the format for the page-directory entries when 4-MByte pagesand 36-bit physical addresses are being used. Section 3.7.6, “Page-Directory andPage-Table Entries” describes the functions of the flags and fields in bits 0through 11.Vol. 3 3-41PROTECTED-MODE MEMORY MANAGEMENTPage-Directory Entry (4-MByte Page)3122 21Page Base Address(Bits 22 Through 31)17 16Reserved13 12 11PAT9 8 7 6 5 4 3 2 1 0P P U RAvail. G P D A C W / / PSD T S WPage Base Address (Bits 32 Through 35)Page Attribute Table IndexAvailable for system programmer’s useGlobal pagePage size (must be set to 1)DirtyAccessedCache disabledWrite-throughUser/SupervisorRead/WritePresentFigure 3-23.
Format of Page-Directory Entries for 4-MByte Pages and36-Bit Physical Addresses3.10PAE-ENABLED PAGING IN IA-32E MODEIntel 64 architecture expands physical address extension (PAE) paging structures topotentially support mapping a 64-bit linear address to a 52-bit physical address. Inthe first implementation of Intel 64 architecture, PAE paging structures supporttranslation of a 48-bit linear address into a 40-bit physical address.When IA-32e mode is enabled, linear address to physical address translation isdifferent than in PAE-enabled protected mode.
Address translation from a linearaddress to a physical address uses up to four levels of paging data structures. A newpage mapping table, the page map level 4 table (PML4 table), is added on top of thepage director pointer table.Prior to activating IA-32e mode, PAE must be enabled by setting CR4.PAE = 1. PAEexpands the size of page-directory entries (PDE) and page-table entries (PTE) from32 bits to 64 bits. This change is made to support physical-address sizes of greaterthan 32 bits.
An attempt to activate IA-32e mode prior to enabling PAE results in ageneral-protection exception, #GP.PML4 tables are used in page translation only in IA-32e mode. They are not usedwhen IA-32e mode is disabled, whether or not PAE is enabled. The existing pagedirectory pointer table is expanded to 512 eight-byte entries from four entries. As aresult, nine bits of the linear address are used to index into a PDP table rather thantwo bits.
The size of the page-directory entry (PDE) table and page-table entry (PTE)table remains 512 eight-byte entries, each indexed by nine linear-address bits. Thetotal of linear-address index bits into the collection of paging data structures (PML43-42 Vol. 3PROTECTED-MODE MEMORY MANAGEMENT+ PDP + PDE + PTE + page offset) becomes 48. The method for translating the highorder 16 linear-address bits into a physical address is currently reserved.The PS flag in the page directory entry (PDE.PS) selects between 4-KByte and2-MByte page sizes. Because PDE.PS is used to control large page selection, theCR4.PSE bit is ignored.3.10.1IA-32e Mode Linear Address Translation (4-KByte Pages)Figure 3-24 shows the PML4, page-directory-pointer, page-directory, and page-tablehierarchy when mapping linear addresses to 4-KByte pages in IA-32e mode.
Thispaging method can be used to address up to 236 pages, which spans a linear addressspace of 248 bytes.To select the various table entries, linear addresses are divided into five sections:•PML4-table entry — Bits 47:39 provide an offset to an entry in the PML4 table.The selected entry provides the base physical address of a page directory pointertable.•Page-directory-pointer-table entry — Bits 38:30 provide an offset to anentry in the page-directory-pointer table. The selected entry provides the basephysical address of a page directory table.•Page-directory entry — Bits 29:21 provide an offset to an entry in the selectedpage directory.
The selected entry provides the base physical address of a pagetable.•Page-table entry — Bits 20:12 provide an offset to an entry in the selectedpage table. This entry provides the base physical address of a page in physicalmemory.•Page offset — Bits 11:0 provide an offset to a physical address in the page.Vol. 3 3-43PROTECTED-MODE MEMORY MANAGEMENTLinear Address39 386348 4730 29Sign ExtendedPML4DirectoryDirectory Ptr21 20Table912 11Offset99012 4-KByte PagePhysical AddrPage-Table EntryPage-DirectoryPointer TableDirectory Entry28Page TablePage-DirectoryDir.
Pointer Entry9512 PML4 *512 PDPTE ∗ 512 PDE ∗ 512 PTE = 236 PagesPML4 Entry401CR3 (PML4)NOTES:1. 40 bits aligned onto a 4-KByte boundaryFigure 3-24. IA-32e Mode Paging Structures (4-KByte Pages)3.10.2IA-32e Mode Linear Address Translation (2-MByte Pages)Figure 3-25 shows the PML4 table, page-directory-pointer, and page-directory hierarchy when mapping linear addresses to 2-MByte pages in IA-32e mode. Thismethod can be used to address up to 227 pages, which spans a linear address spaceof 248 bytes.The 2-MByte page size is selected by setting the page size (PS) flag in a page-directory entry (see Figure 3-14). The PSE flag in control register CR4 has no affect on thepage size when PAE is enabled.
With the PS flag set, a linear address is divided intofour sections:•PML4-table entry — Bits 47:39 provide an offset to an entry in the PML4 table.The selected entry provides the base physical address of a page directory pointertable.3-44 Vol. 3PROTECTED-MODE MEMORY MANAGEMENT•Page-directory-pointer-table entry — Bits 38:30 provide an offset to anentry in the page-directory-pointer table. The selected entry provides the basephysical address of a page directory.•Page-directory entry — Bits 29:21 provide an offset to an entry in the pagedirectory. The selected entry provides the base physical address of a 2-MBytepage.•Page offset — Bits 20:0 provides an offset to a physical address in the page.Linear Address39 386348 4730 29Sign ExtendedPML4DirectoryDirectory Ptr21 200Offset21992-MByte PagePhysical AddrPage-DirectoryPointer TableDirectory Entry19Page-DirectoryDir.
Pointer Entry9512 PML4 *512 PDPTE ∗ 512 PDE = 227 PagesPML4 Entry401CR3 (PML4)NOTE:1. 40 bits aligned onto a 4-KByte boundaryFigure 3-25. IA-32e Mode Paging Structures (2-MByte pages)3.10.3Enhanced Paging Data StructuresFigure 3-26 shows the format for the PML4 table, page-directory-pointer table,page-directory and page-table entries when 4-KByte pages are used in IA-32emode. Figure 3-27 shows the format for the PML4 table, the page-directorypointer table and page-directory entries when 2-MByte pages are used in IA-32emode.Vol.
3 3-45PROTECTED-MODE MEMORY MANAGEMENTExcept for the PML4 table; enhanced formats of page-directory-pointer table, pagedirectory, and page-table entries are also used in enhanced legacy PAE-enabledpaging on processors that support Intel 64 architecture (see Section 3.8.1,“Enhanced Legacy PAE Paging”).Page-Map-Level-4-Table Entry63 62EXB5139AvailReserved (set to 0)3132Base Address12 11AvailPML4 Base Address6 5 4PRsvd. A CD9 83PWT2U/S1 0R/ PWPage-Directory-Pointer-Table Entry63 62EXB51Avail39Reserved (set to 0)3112 116 5 4PRsvd A CD9 8AvailPage-Directory Base Address3PWT2U/S1 0R/ PWPage-Directory Entry (4-KByte Page Table)63 62EXB32Base Address51Avail39Base AddressReserved (set to 0)313212 119 8 7 6 5 4PAvail 0 0 0 A CDPage-Table Base Address3PWT2U/S1 0R/ PWPage-Table Entry (4-KByte Page)63 62EXB51Avail39Reserved (set to 0)3132Base Address12 11Page Base Address9 8 7 6 5 4PPAvail G A D A CTD3PWT2 1 0U R/ / PS WFigure 3-26.
Format of Paging Structure Entries for 4-KByte Pages in IA-32e ModeExcept for bit 63, functions of the flags in these entries are as described in Section3.7.6, “Page-Directory and Page-Table Entries”. The differences are:••A PML4 table entry and a page-directory-pointer-table entry are added.Entries are increased from 32 bits to 64 bits.3-46 Vol.
3PROTECTED-MODE MEMORY MANAGEMENT•The maximum number of entries in a page directory, page table, or PML4 table is512.•The P, R/W, U/S, PWT, PCD, and A flags are implemented uniformly across all fourlevels.•The base physical address field in each entry is extended to 28 bits if theprocessor’s implementation supports a 40-bit physical address.••Bits 62:52 are available for use by system programmers.Bit 63 is the execute-disable bit if the execute-disable bit feature is supported inthe processor. If the feature is not supported, bit 63 is reserved. The functionalityof the execute disable bit is described in Section 4.11, “Page-Level Protection”. Itrequires both PAE and enhanced paging data structures. Note that the executedisable bit can provide page protection in 32-bit PAE mode and IA-32e mode.Page-Map-Level-4-Table Entry*63 62EXB5139Avail32Base AddressReserved (set to 0)3112 11PML4 Base Address6 5 4 3 2 1 09 8AvailP P U RRsvd.
A C W / / PD T S WPage-Directory-Pointer-Table Entry*63 62EXB51Avail39Reserved (set to 0)3112 116 5 4 3 2 1 09 8AvailPage-Directory Base Address32Base AddressP P U RRsvd A C W / / PD T S WPage-Directory Entry (2-MByte Page)63 62EXBAvail31Page Base AddressReserved (set to 0)21 20Reserved (set to323952 51Page Base Address13 12 119 8 7 6 5 4PP0) A Avail G 1 D A CTD3PWT2U/S1 0R/ PW* Identical to the structures in 4-KByte pages.Figure 3-27. Format of Paging Structure Entries for 2-MByte Pages in IA-32e ModeVol. 3 3-47PROTECTED-MODE MEMORY MANAGEMENT3.10.3.1Intel® 64 Processors and Reserved Bit CheckingOn processors supporting Intel 64 architecture and/or supporting the execute disablebit, the processor enforces reserved bit checking on paging mode specific bits.Table 3-4 shows the reserved bits that are checked on Intel 64 processors whenexecute disable bit checking is either disabled or not supported.
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