Volume 3A System Programming Guide_ Part 1 (794103), страница 34
Текст из файла (страница 34)
This is the address space that the processor can address onits address bus. This address space is flat (unsegmented), with addresses rangingcontinuously from 0 to FFFFFFFFH. This physical address space can be mapped toread-write memory, read-only memory, and memory mapped I/O. The memorymapping facilities described in this chapter can be used to divide this physicalmemory up into segments and/or pages.Starting with the Pentium Pro processor, the IA-32 architecture also supports anextension of the physical address space to 236 bytes (64 GBytes); with a maximumphysical address of FFFFFFFFFH.
This extension is invoked in either of two ways:•Using the physical address extension (PAE) flag, located in bit 5 of controlregister CR4.•Using the 36-bit page size extension (PSE-36) feature (introduced in the PentiumIII processors).See Section 3.8, “36-Bit Physical Addressing Using the PAE Paging Mechanism” andSection 3.9, “36-Bit Physical Addressing Using the PSE-36 Paging Mechanism” formore information about 36-bit physical addressing.Vol. 3 3-7PROTECTED-MODE MEMORY MANAGEMENT3.3.1Intel® 64 Processors and Physical Address SpaceOn processors that support Intel 64 architecture (CPUID.80000001:EDX[29] = 1),the size of the physical address range is implementation-specific and indicated byCPUID.80000008H:EAX[bits 7-0].For the format of information returned in EAX, see “CPUID—CPU Identification” inChapter 3 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual,Volume 2A.
See also: Section 3.8.1, “Enhanced Legacy PAE Paging.”3.4LOGICAL AND LINEAR ADDRESSESAt the system-architecture level in protected mode, the processor uses two stages ofaddress translation to arrive at a physical address: logical-address translation andlinear address space paging.Even with the minimum use of segments, every byte in the processor’s addressspace is accessed with a logical address. A logical address consists of a 16-bitsegment selector and a 32-bit offset (see Figure 3-5).
The segment selector identifies the segment the byte is located in and the offset specifies the location of the bytein the segment relative to the base address of the segment.The processor translates every logical address into a linear address.
A linear addressis a 32-bit address in the processor’s linear address space. Like the physical addressspace, the linear address space is a flat (unsegmented), 232-byte address space,with addresses ranging from 0 to FFFFFFFFH. The linear address space contains allthe segments and system tables defined for a system.To translate a logical address into a linear address, the processor does the following:1. Uses the offset in the segment selector to locate the segment descriptor for thesegment in the GDT or LDT and reads it into the processor.
(This step is neededonly when a new segment selector is loaded into a segment register.)2. Examines the segment descriptor to check the access rights and range of thesegment to insure that the segment is accessible and that the offset is within thelimits of the segment.3. Adds the base address of the segment from the segment descriptor to the offsetto form a linear address.3-8 Vol. 3PROTECTED-MODE MEMORY MANAGEMENTLogicalAddress031(63)Offset (Effective Address)150Seg. SelectorDescriptor TableSegmentDescriptorBase Address+31(63)0Linear AddressFigure 3-5. Logical Address to Linear Address TranslationIf paging is not used, the processor maps the linear address directly to a physicaladdress (that is, the linear address goes out on the processor’s address bus).
If thelinear address space is paged, a second level of address translation is used to translate the linear address into a physical address.See also: Section 3.6, “Paging (Virtual Memory) Overview”.3.4.1Logical Address Translation in IA-32e ModeIn IA-32e mode, an Intel 64 processor uses the steps described above to translate alogical address to a linear address.
In 64-bit mode, the offset and base address of thesegment are 64-bits instead of 32 bits. The linear address format is also 64 bits wideand is subject to the canonical form requirement.Each code segment descriptor provides an L bit. This bit allows a code segment toexecute 64-bit code or legacy 32-bit code by code segment.3.4.2Segment SelectorsA segment selector is a 16-bit identifier for a segment (see Figure 3-6). It does notpoint directly to the segment, but instead points to the segment descriptor thatdefines the segment. A segment selector contains the following items:Index(Bits 3 through 15) — Selects one of 8192 descriptors in the GDT orLDT.
The processor multiplies the index value by 8 (the number ofbytes in a segment descriptor) and adds the result to the base addressof the GDT or LDT (from the GDTR or LDTR register, respectively).Vol. 3 3-9PROTECTED-MODE MEMORY MANAGEMENTTI (table indicator) flag(Bit 2) — Specifies the descriptor table to use: clearing this flagselects the GDT; setting this flag selects the current LDT.153 2 1 0IndexT RPLITable Indicator0 = GDT1 = LDTRequested Privilege Level (RPL)Figure 3-6.
Segment SelectorRequested Privilege Level (RPL)(Bits 0 and 1) — Specifies the privilege level of the selector. The privilege level can range from 0 to 3, with 0 being the most privilegedlevel. See Section 4.5, “Privilege Levels”, for a description of the relationship of the RPL to the CPL of the executing program (or task) andthe descriptor privilege level (DPL) of the descriptor the segmentselector points to.The first entry of the GDT is not used by the processor.
A segment selector that pointsto this entry of the GDT (that is, a segment selector with an index of 0 and the TI flagset to 0) is used as a “null segment selector.” The processor does not generate anexception when a segment register (other than the CS or SS registers) is loaded witha null selector. It does, however, generate an exception when a segment registerholding a null selector is used to access memory. A null selector can be used toinitialize unused segment registers.
Loading the CS or SS register with a nullsegment selector causes a general-protection exception (#GP) to be generated.Segment selectors are visible to application programs as part of a pointer variable,but the values of selectors are usually assigned or modified by link editors or linkingloaders, not application programs.3.4.3Segment RegistersTo reduce address translation time and coding complexity, the processor providesregisters for holding up to 6 segment selectors (see Figure 3-7). Each of thesesegment registers support a specific kind of memory reference (code, stack, ordata). For virtually any kind of program execution to take place, at least the codesegment (CS), data-segment (DS), and stack-segment (SS) registers must beloaded with valid segment selectors.
The processor also provides three additionaldata-segment registers (ES, FS, and GS), which can be used to make additional datasegments available to the currently executing program (or task).3-10 Vol. 3PROTECTED-MODE MEMORY MANAGEMENTFor a program to access a segment, the segment selector for the segment must havebeen loaded in one of the segment registers. So, although a system can define thousands of segments, only 6 can be available for immediate use. Other segments canbe made available by loading their segment selectors into these registers duringprogram execution.Visible PartSegment SelectorHidden PartBase Address, Limit, Access InformationCSSSDSESFSGSFigure 3-7.
Segment RegistersEvery segment register has a “visible” part and a “hidden” part. (The hidden part issometimes referred to as a “descriptor cache” or a “shadow register.”) When asegment selector is loaded into the visible part of a segment register, the processoralso loads the hidden part of the segment register with the base address, segmentlimit, and access control information from the segment descriptor pointed to by thesegment selector.
The information cached in the segment register (visible andhidden) allows the processor to translate addresses without taking extra bus cyclesto read the base address and limit from the segment descriptor. In systems in whichmultiple processors have access to the same descriptor tables, it is the responsibilityof software to reload the segment registers when the descriptor tables are modified.If this is not done, an old segment descriptor cached in a segment register might beused after its memory-resident version has been modified.Two kinds of load instructions are provided for loading the segment registers:1. Direct load instructions such as the MOV, POP, LDS, LES, LSS, LGS, and LFSinstructions.
These instructions explicitly reference the segment registers.2. Implied load instructions such as the far pointer versions of the CALL, JMP, andRET instructions, the SYSENTER and SYSEXIT instructions, and the IRET, INTn,INTO and INT3 instructions. These instructions change the contents of the CSregister (and sometimes other segment registers) as an incidental part of theiroperation.The MOV instruction can also be used to store visible part of a segment register in ageneral-purpose register.Vol. 3 3-11PROTECTED-MODE MEMORY MANAGEMENT3.4.4Segment Loading Instructions in IA-32e ModeBecause ES, DS, and SS segment registers are not used in 64-bit mode, their fields(base, limit, and attribute) in segment descriptor registers are ignored.
Some formsof segment load instructions are also invalid (for example, LDS, POP ES). Addresscalculations that reference the ES, DS, or SS segments are treated as if the segmentbase is zero.The processor checks that all linear-address references are in canonical form insteadof performing limit checks. Mode switching does not change the contents of thesegment registers or the associated descriptor registers. These registers are also notchanged during 64-bit mode execution, unless explicit segment loads are performed.In order to set up compatibility mode for an application, segment-load instructions(MOV to Sreg, POP Sreg) work normally in 64-bit mode.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
