Volume 3A System Programming Guide_ Part 1 (794103), страница 32
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The processor generates aspecial bus cycle to indicate that the halt mode has been entered.Hardware may respond to this signal in a number of ways. An indicator light on thefront panel may be turned on. An NMI interrupt for recording diagnostic informationmay be generated. Reset initialization may be invoked (note that the BINIT# pin wasintroduced with the Pentium Pro processor). If any non-wake events are pendingduring shutdown, they will be handled after the wake event from shutdown isprocessed (for example, A20M# interrupts).Vol. 3 2-29SYSTEM ARCHITECTURE OVERVIEWThe LOCK prefix invokes a locked (atomic) read-modify-write operation when modifying a memory operand. This mechanism is used to allow reliable communicationsbetween processors in multiprocessor systems, as described below:•In the Pentium processor and earlier IA-32 processors, the LOCK prefix causesthe processor to assert the LOCK# signal during the instruction.
This alwayscauses an explicit bus lock to occur.•In the Pentium 4, Intel Xeon, and P6 family processors, the locking operation ishandled with either a cache lock or bus lock. If a memory access is cacheable andaffects only a single cache line, a cache lock is invoked and the system bus andthe actual memory location in system memory are not locked during theoperation.
Here, other Pentium 4, Intel Xeon, or P6 family processors on the buswrite-back any modified data and invalidate their caches as necessary tomaintain system memory coherency. If the memory access is not cacheableand/or it crosses a cache line boundary, the processor’s LOCK# signal is assertedand the processor does not respond to requests for bus control during the lockedoperation.The RSM (return from SMM) instruction restores the processor (from a contextdump) to the state it was in prior to an system management mode (SMM) interrupt.2.6.6Reading Performance-Monitoring and Time-Stamp CountersThe RDPMC (read performance-monitoring counter) and RDTSC (read time-stampcounter) instructions allow application programs to read the processor’s performance-monitoring and time-stamp counters, respectively.
Pentium 4 and Intel Xeonprocessors have eighteen 40-bit performance-monitoring counters; P6 familyprocessors have two 40-bit counters.Use these counters to record either the occurrence or duration of events. Events thatcan be monitored are model specific; they may include the number of instructionsdecoded, interrupts received, or the number of cache loads.
Individual counters canbe set up to monitor different events. Use the system instruction WRMSR to set upvalues in the one of the 45 ESCRs and one of the 18 CCCR MSRs (for Pentium 4 andIntel Xeon processors); or in the PerfEvtSel0 or the PerfEvtSel1 MSR (for the P6family processors). The RDPMC instruction loads the current count from the selectedcounter into the EDX:EAX registers.The time-stamp counter is a model-specific 64-bit counter that is reset to zero eachtime the processor is reset. If not reset, the counter will increment ~9.5 x 1016times per year when the processor is operating at a clock rate of 3GHz.
At thisclock frequency, it would take over 190 years for the counter to wrap around. TheRDTSC instruction loads the current count of the time-stamp counter into theEDX:EAX registers.See Section 18.11, “Performance Monitoring Overview,” and Section 18.10, “TimeStamp Counter,” for more information about the performance monitoring and timestamp counters.2-30 Vol. 3SYSTEM ARCHITECTURE OVERVIEWThe RDTSC instruction was introduced into the IA-32 architecture with the Pentiumprocessor.
The RDPMC instruction was introduced into the IA-32 architecture with thePentium Pro processor and the Pentium processor with MMX technology. EarlierPentium processors have two performance-monitoring counters, but they can beread only with the RDMSR instruction, and only at privilege level 0.2.6.6.1Reading Counters in 64-Bit ModeIn 64-bit mode, RDTSC operates the same as in protected mode. The count in thetime-stamp counter is stored in EDX:EAX (or RDX[31:0]:RAX[31:0] withRDX[63:32]:RAX[63:32] cleared).RDPMC requires an index to specify the offset of the performance-monitoringcounter.
In 64-bit mode for Pentium 4 or Intel Xeon processor families, the index isspecified in ECX[30:0]. The current count of the performance-monitoring counter isstored in EDX:EAX (or RDX[31:0]:RAX[31:0] with RDX[63:32]:RAX[63:32]cleared).2.6.7Reading and Writing Model-Specific RegistersThe RDMSR (read model-specific register) and WRMSR (write model-specificregister) instructions allow a processor’s 64-bit model-specific registers (MSRs) to beread and written, respectively. The MSR to be read or written is specified by the valuein the ECX register.RDMSR reads the value from the specified MSR to the EDX:EAX registers; WRMSRwrites the value in the EDX:EAX registers to the specified MSR.
RDMSR and WRMSRwere introduced into the IA-32 architecture with the Pentium processor.See Section 9.4, “Model-Specific Registers (MSRs),” for more information.2.6.7.1Reading and Writing Model-Specific Registers in 64-Bit ModeRDMSR and WRMSR require an index to specify the address of an MSR. In 64-bitmode, the index is 32 bits; it is specified using ECX.Vol. 3 2-31SYSTEM ARCHITECTURE OVERVIEW2-32 Vol. 3CHAPTER 3PROTECTED-MODE MEMORY MANAGEMENTThis chapter describes the Intel 64 and IA-32 architecture’s protected-mode memorymanagement facilities, including the physical memory requirements, segmentationmechanism, and paging mechanism.See also: Chapter 4, “Protection” (for a description of the processor’s protectionmechanism) and Chapter 15, “8086 Emulation” (for a description of memoryaddressing protection in real-address and virtual-8086 modes).3.1MEMORY MANAGEMENT OVERVIEWThe memory management facilities of the IA-32 architecture are divided into twoparts: segmentation and paging.
Segmentation provides a mechanism of isolatingindividual code, data, and stack modules so that multiple programs (or tasks) canrun on the same processor without interfering with one another. Paging provides amechanism for implementing a conventional demand-paged, virtual-memory systemwhere sections of a program’s execution environment are mapped into physicalmemory as needed. Paging can also be used to provide isolation between multipletasks. When operating in protected mode, some form of segmentation must be used.There is no mode bit to disable segmentation. The use of paging, however, isoptional.These two mechanisms (segmentation and paging) can be configured to supportsimple single-program (or single-task) systems, multitasking systems, or multipleprocessor systems that used shared memory.As shown in Figure 3-1, segmentation provides a mechanism for dividing theprocessor’s addressable memory space (called the linear address space) intosmaller protected address spaces called segments.
Segments can be used to holdthe code, data, and stack for a program or to hold system data structures (such as aTSS or LDT). If more than one program (or task) is running on a processor, eachprogram can be assigned its own set of segments. The processor then enforces theboundaries between these segments and insures that one program does not interferewith the execution of another program by writing into the other program’s segments.The segmentation mechanism also allows typing of segments so that the operationsthat may be performed on a particular type of segment can be restricted.All the segments in a system are contained in the processor’s linear address space.To locate a byte in a particular segment, a logical address (also called a far pointer)must be provided. A logical address consists of a segment selector and an offset.
Thesegment selector is a unique identifier for a segment. Among other things it providesan offset into a descriptor table (such as the global descriptor table, GDT) to a datastructure called a segment descriptor. Each segment has a segment descriptor, whichspecifies the size of the segment, the access rights and privilege level for theVol. 3 3-1PROTECTED-MODE MEMORY MANAGEMENTsegment, the segment type, and the location of the first byte of the segment in thelinear address space (called the base address of the segment). The offset part of thelogical address is added to the base address for the segment to locate a byte withinthe segment.
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