Volume 3A System Programming Guide_ Part 1 (794103), страница 28
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This modeprovides an operating system or executive with a transparent mechanism forimplementing power management and OEM differentiation features. SMM isentered through activation of an external system interrupt pin (SMI#), whichgenerates a system management interrupt (SMI). In SMM, the processorswitches to a separate address space while saving the context of the currently2-10 Vol.
3SYSTEM ARCHITECTURE OVERVIEWrunning program or task. SMM-specific code may then be executed transparently.Upon returning from SMM, the processor is placed back into its state prior to theSMI.•Virtual-8086 mode — In protected mode, the processor supports a quasioperating mode known as virtual-8086 mode. This mode allows the processorexecute 8086 software in a protected, multitasking environment.Intel 64 architecture supports all operating modes of IA-32 architecture and IA-32emodes:•IA-32e mode — In IA-32e mode, the processor supports two sub-modes:compatibility mode and 64-bit mode. 64-bit mode provides 64-bit linearaddressing and support for physical address space larger than 64 GBytes.Compatibility mode allows most legacy protected-mode applications to rununchanged.Figure 2-3 shows how the processor moves between operating modes.SMI#Real-AddressModeReset orPE=0PE=1ResetorRSMSMI#ResetProtected ModeSee**VM=0RSMLME=1, CR0.PG=1*SMI#IA-32eModeRSMSystemManagementModeVM=1* See Section 9.8.5Virtual-8086ModeSMI#** See Section 9.8.5.4RSMFigure 2-3.
Transitions Among the Processor’s Operating ModesThe processor is placed in real-address mode following power-up or a reset. The PEflag in control register CR0 then controls whether the processor is operating in realaddress or protected mode. See also: Section 9.9, “Mode Switching.”The VM flag in the EFLAGS register determines whether the processor is operating inprotected mode or virtual-8086 mode. Transitions between protected mode andVol. 3 2-11SYSTEM ARCHITECTURE OVERVIEWvirtual-8086 mode are generally carried out as part of a task switch or a return froman interrupt or exception handler.
See also: Section 15.2.5, “Entering Virtual-8086Mode.”The LMA bit (IA32_EFER.LMA.LMA[bit 10]) determines whether the processor isoperating in IA-32e mode. When running in IA-32e mode, 64-bit or compatibilitysub-mode operation is determined by CS.L bit of the code segment. The processorenters into IA-32e mode from protected mode by enabling paging and setting theLME bit (IA32_EFER.LME[bit 8]). See also: Chapter 9, “Processor Management andInitialization.”The processor switches to SMM whenever it receives an SMI while the processor is inreal-address, protected, virtual-8086, or IA-32e modes. Upon execution of the RSMinstruction, the processor always returns to the mode it was in when the SMIoccurred.2.3SYSTEM FLAGS AND FIELDS IN THE EFLAGSREGISTERThe system flags and IOPL field of the EFLAGS register control I/O, maskable hardware interrupts, debugging, task switching, and the virtual-8086 mode (seeFigure 2-4).
Only privileged code (typically operating system or executive code)should be allowed to modify these bits.The system flags and IOPL are:TFTrap (bit 8) — Set to enable single-step mode for debugging; clear todisable single-step mode. In single-step mode, the processor generates adebug exception after each instruction. This allows the execution state of aprogram to be inspected after each instruction.
If an application programsets the TF flag using a POPF, POPFD, or IRET instruction, a debug exceptionis generated after the instruction that follows the POPF, POPFD, or IRET.2-12 Vol. 3SYSTEM ARCHITECTURE OVERVIEW3122 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Reserved (set to 0)V VI I I A V R 0 NTC M FDP FIOPLO D I T S ZPCAF F F F F F 0 F 0 F 1 FID — Identification FlagVIP — Virtual Interrupt PendingVIF — Virtual Interrupt FlagAC — Alignment CheckVM — Virtual-8086 ModeRF — Resume FlagNT — Nested Task FlagIOPL— I/O Privilege LevelIF — Interrupt Enable FlagTF — Trap FlagReservedFigure 2-4. System Flags in the EFLAGS RegisterIFInterrupt enable (bit 9) — Controls the response of the processor tomaskable hardware interrupt requests (see also: Section 5.3.2, “MaskableHardware Interrupts”). The flag is set to respond to maskable hardwareinterrupts; cleared to inhibit maskable hardware interrupts. The IF flag doesnot affect the generation of exceptions or nonmaskable interrupts (NMIinterrupts).
The CPL, IOPL, and the state of the VME flag in control registerCR4 determine whether the IF flag can be modified by the CLI, STI, POPF,POPFD, and IRET.IOPLI/O privilege level field (bits 12 and 13) — Indicates the I/O privilegelevel (IOPL) of the currently running program or task. The CPL of thecurrently running program or task must be less than or equal to the IOPL toaccess the I/O address space.
This field can only be modified by the POPFand IRET instructions when operating at a CPL of 0.The IOPL is also one of the mechanisms that controls the modification of theIF flag and the handling of interrupts in virtual-8086 mode when virtualmode extensions are in effect (when CR4.VME = 1). See also: Chapter 13,“Input/Output,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.NTNested task (bit 14) — Controls the chaining of interrupted and calledtasks. The processor sets this flag on calls to a task initiated with a CALLinstruction, an interrupt, or an exception. It examines and modifies this flagon returns from a task initiated with the IRET instruction.
The flag can beexplicitly set or cleared with the POPF/POPFD instructions; however,Vol. 3 2-13SYSTEM ARCHITECTURE OVERVIEWchanging to the state of this flag can generate unexpected exceptions inapplication programs.See also: Section 6.4, “Task Linking.”RFResume (bit 16) — Controls the processor’s response to instruction-breakpoint conditions. When set, this flag temporarily disables debug exceptions(#DB) from being generated for instruction breakpoints (although otherexception conditions can cause an exception to be generated).
When clear,instruction breakpoints will generate debug exceptions.The primary function of the RF flag is to allow the restarting of an instructionfollowing a debug exception that was caused by an instruction breakpointcondition. Here, debug software must set this flag in the EFLAGS image onthe stack just prior to returning to the interrupted program with IRETD (toprevent the instruction breakpoint from causing another debug exception).The processor then automatically clears this flag after the instructionreturned to has been successfully executed, enabling instruction breakpointfaults again.See also: Section 18.3.1.1, “Instruction-Breakpoint Exception Condition.”VMVirtual-8086 mode (bit 17) — Set to enable virtual-8086 mode; clear toreturn to protected mode.See also: Section 15.2.1, “Enabling Virtual-8086 Mode.”ACAlignment check (bit 18) — Set this flag and the AM flag in control registerCR0 to enable alignment checking of memory references; clear the AC flagand/or the AM flag to disable alignment checking.
An alignment-checkexception is generated when reference is made to an unaligned operand,such as a word at an odd byte address or a doubleword at an address whichis not an integral multiple of four. Alignment-check exceptions are generatedonly in user mode (privilege level 3). Memory references that default to privilege level 0, such as segment descriptor loads, do not generate this exception even when caused by instructions executed in user-mode.The alignment-check exception can be used to check alignment of data. Thisis useful when exchanging data with processors which require all data to bealigned. The alignment-check exception can also be used by interpreters toflag some pointers as special by misaligning the pointer.
This eliminatesoverhead of checking each pointer and only handles the special pointer whenused.VIFVirtual Interrupt (bit 19) — Contains a virtual image of the IF flag. Thisflag is used in conjunction with the VIP flag. The processor only recognizesthe VIF flag when either the VME flag or the PVI flag in control register CR4 isset and the IOPL is less than 3.
(The VME flag enables the virtual-8086 modeextensions; the PVI flag enables the protected-mode virtual interrupts.)See also: Section 15.3.3.5, “Method 6: Software Interrupt Handling,” andSection 15.4, “Protected-Mode Virtual Interrupts.”2-14 Vol. 3SYSTEM ARCHITECTURE OVERVIEWVIPVirtual interrupt pending (bit 20) — Set by software to indicate that aninterrupt is pending; cleared to indicate that no interrupt is pending. This flagis used in conjunction with the VIF flag.
The processor reads this flag butnever modifies it. The processor only recognizes the VIP flag when either theVME flag or the PVI flag in control register CR4 is set and the IOPL is less than3. The VME flag enables the virtual-8086 mode extensions; the PVI flagenables the protected-mode virtual interrupts.See Section 15.3.3.5, “Method 6: Software Interrupt Handling,” and Section15.4, “Protected-Mode Virtual Interrupts.”ID2.3.1Identification (bit 21). — The ability of a program or procedure to set orclear this flag indicates support for the CPUID instruction.System Flags and Fields in IA-32e ModeIn 64-bit mode, the RFLAGS register expands to 64 bits with the upper 32 bitsreserved. System flags in RFLAGS (64-bit mode) or EFLAGS (compatibility mode)are shown in Figure 2-4.In IA-32e mode, the processor does not allow the VM bit to be set because virtual8086 mode is not supported (attempts to set the bit are ignored).
Also, the processorwill not set the NT bit. The processor does, however, allow software to set the NT bit(note that an IRET causes a general protection fault in IA-32e mode if the NT bit isset).In IA-32e mode, the SYSCALL/SYSRET instructions have a programmable method ofspecifying which bits are cleared in RFLAGS/EFLAGS. These instructions save/restoreEFLAGS/RFLAGS.2.4MEMORY-MANAGEMENT REGISTERSThe processor provides four memory-management registers (GDTR, LDTR, IDTR,and TR) that specify the locations of the data structures which control segmentedmemory management (see Figure 2-5).
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