Volume 2 System Programming (794096), страница 32
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A #GP occurs if software attempts to load the CS register with a nullselector or if software attempts to load the SS register with a null selector in non 64-bit mode or at CPL3.4.5.2 Segment RegistersSix 16-bit segment registers are provided for referencing up to six segments at one time.
All softwaretasks require segment selectors to be loaded in the CS and SS registers. Use of the DS, ES, FS, and GSsegments is optional, but nearly all software accesses data and therefore requires a selector in the DSregister. Table 4-1 on page 69 lists the supported segment registers and their functions.68Segmented Virtual Memory24593—Rev. 3.13—July 2007Table 4-1.AMD64 TechnologySegment RegistersSegmentRegisterSegment Register FunctionCSReferences code-segment descriptor entryDSReferences default data-segment descriptor entryESReferences optional data-segment descriptor entryFSReferences optional data-segment descriptor entryGSReferences optional data-segment descriptor entrySSReferences stack segment descriptor entryThe processor maintains a hidden portion of the segment register in addition to the selector valueloaded by software.
This hidden portion contains the values found in the descriptor-table entryreferenced by the segment selector. The processor loads the descriptor-table entry into the hiddenportion when the segment register is loaded. By keeping the corresponding descriptor-table entry inhardware, performance is optimized for the majority of memory references.Figure 4-4 shows the format of the visible and hidden portions of the segment register. Except for theFS and GS segment base, software cannot directly read or write the hidden portion (shown as grayshaded boxes in Figure 4-4).SelectorSegment Attributes32-Bit Segment Limit32-Bit Segment Base AddressHidden From SoftwareFigure 4-4.513-221.epsSegment-Register FormatCS Register. The CS register contains the segment selector referencing the current code-segmentdescriptor entry.
All instruction fetches reference the CS descriptor. When a new selector is loaded intothe CS register, the current-privilege level (CPL) of the processor is set to that of the CS-segmentdescriptor-privilege level (DPL).Data-Segment Registers. The DS register contains the segment selector referencing the defaultdata-segment descriptor entry. The SS register contains the stack-segment selector. The ES, FS, andGS registers are optionally loaded with segment selectors referencing other data segments.
Dataaccesses default to referencing the DS descriptor except in the following two cases:Segmented Virtual Memory69AMD64 Technology••24593—Rev. 3.13—July 2007The ES descriptor is referenced for string-instruction destinations.The SS descriptor is referenced for stack operations.4.5.3 Segment Registers in 64-Bit ModeCS Register in 64-Bit Mode.
In 64-bit mode, most of the hidden portion of the CS register isignored. Only the L (long), D (default operation size), and DPL (descriptor privilege-level) attributesare recognized by 64-bit mode. Address calculations assume a CS.base value of 0. CS references donot check the CS.limit value, but instead check that the effective address is in canonical form.DS, ES, and SS Registers in 64-Bit Mode.
In 64-bit mode, the contents of the ES, DS, and SSsegment registers are ignored. All fields (base, limit, and attribute) in the hidden portion of the segmentregisters are ignored.Address calculations in 64-bit mode that reference the ES, DS, or SS segments are treated as if thesegment base is 0. Instead of performing limit checks, the processor checks that all virtual-addressreferences are in canonical form.Neither enabling and activating long mode nor switching between 64-bit and compatibility modeschanges the contents of the visible or hidden portions of the segment registers.
These registers remainunchanged during 64-bit mode execution unless explicit segment loads are performed.FS and GS Registers in 64-Bit Mode. Unlike the CS, DS, ES, and SS segments, the FS and GSsegment overrides can be used in 64-bit mode. When FS and GS segment overrides are used in 64-bitmode, their respective base addresses are used in the effective-address (EA) calculation.
The completeEA calculation then becomes (FS or GS).base + base + (scale ∗ index) + displacement. The FS.baseand GS.base values are also expanded to the full 64-bit virtual-address size, as shown in Figure 4-5.The resulting EA calculation is allowed to wrap across positive and negative addresses.SelectorSegment Attributes32-Bit Segment Limit64-Bit Segment Base AddressHidden from Software and Unused in 64-bit Mode513-267.epsFigure 4-5.
FS and GS Segment-Register Format—64-Bit ModeIn 64-bit mode, FS-segment and GS-segment overrides are not checked for limit or attributes. Instead,the processor checks that all virtual-address references are in canonical form.70Segmented Virtual Memory24593—Rev. 3.13—July 2007AMD64 TechnologySegment register-load instructions (MOV to Sreg and POP Sreg) load only a 32-bit base-address valueinto the hidden portion of the FS and GS segment registers. The base-address bits above the low 32 bitsare cleared to 0 as a result of a segment-register load.To allow loading all 64 bits of the base address, the FS.base and GS.base hidden descriptor-registerfields are mapped to MSRs.
Privileged software (CPL=0) can load the 64-bit base address into FS.baseor GS.base using a single WRMSR instruction. The addresses written into the expanded FS.base andGS.base registers must be in canonical form. A WRMSR instruction that attempts to write a noncanonical address to these registers causes a general-protection exception (#GP) to occur.The FS.base MSR address is C000_0100h while the GS.base MSR address is C000_0101h.When in compatibility mode, the FS and GS overrides operate as defined by the legacy x86architecture regardless of the value loaded into the high 32 bits of the hidden descriptor-register baseaddress field.
Compatibility mode ignores the high 32 bits when calculating an effective address.4.6Descriptor TablesDescriptor tables are used by the segmentation mechanism when protected mode is enabled(CR0.PE=1). These tables hold descriptor entries that describe the location, size, and privilegeattributes of a segment. All memory references in protected mode access a descriptor-table entry.As previously mentioned, there are three types of descriptor tables supported by the x86 segmentationmechanism:•••Global descriptor table (GDT)Local descriptor table (LDT)Interrupt descriptor table (IDT)Software establishes the location of a descriptor table in memory by initializing its correspondingdescriptor-table register. The descriptor-table registers and the descriptor tables are described in thefollowing sections.4.6.1 Global Descriptor TableProtected-mode system software must create a global descriptor table (GDT). The GDT contains codesegment and data-segment descriptor entries (user segments) for segments that can be shared by alltasks.
In addition to the user segments, the GDT can also hold gate descriptors and other systemsegment descriptors. System software can store the GDT anywhere in memory and should protect thesegment containing the GDT from non-privileged software.Segment selectors point to the GDT when the table-index (TI) bit in the selector is cleared to 0. Theselector index portion of the segment selector references a specific entry in the GDT. Figure 4-6 onpage 72 shows how the segment selector indexes into the GDT. One special form of a segment selectoris the null selector.
A null selector points to the first entry in the GDT (the selector index is 0 andTI=0). However, null selectors do not reference memory, so the first GDT entry cannot be used toSegmented Virtual Memory71AMD64 Technology24593—Rev. 3.13—July 2007describe a segment (see “Null Selector” on page 68 for information on using the null selector). Thefirst usable GDT entry is referenced with a selector index of 1.Selector IndexTISegment SelectorGlobal (TI=0)Local (TI=1)Descriptor Table++Selector Index000Unused in GDTDescriptor Table Base AddressDescriptor Table LimitGlobal or Local Descriptor-Table Register513-209.epsFigure 4-6.