Volume 2 System Programming (794096), страница 30
Текст из файла (страница 30)
Two types of machine-check MSRs are shown in Figure 3-10 onpage 57.The first type is global machine-check registers, which perform the following functions:60System Resources24593—Rev. 3.13—July 2007AMD64 TechnologyMCG_CAP Register. This register identifies the machine-check capabilities supported by theprocessor.MCG_CTL Register. This register provides global control over machine-check-error reporting.MCG_STATUS Register. This register reports global status on detected machine-check errors.The second type is error-reporting register banks, which report on machine-check errors associatedwith a specific processor unit (or group of processor units). There can be different numbers of registerbanks for each processor implementation, and each bank is numbered from 0 to i.
The registers in eachbank perform the following functions:MCi_CTL Registers. These registers control error-reporting.MCi_STATUS Registers. These registers report machine-check errors.MCi_ADDR Registers. These registers report the machine-check error address.MCi_MISC Registers. These registers report miscellaneous-error information.Refer to “Using Machine Check Features” on page 265 for more information on using these registers.3.3Processor Feature IdentificationThe CPUID instruction provides information about the processor implementation and its capabilities.Software operating at any privilege level can execute the CPUID instruction to collect this information.After the information is collected, software can be tuned to optimize performance and benefit to users.For example, game software can identify and enable the media capabilities of a particular processorimplementation.The CPUID instruction supports multiple functions, each providing different information about theprocessor implementation, including the vendor, model number, revision (stepping), features, cacheorganization, and name.
The multifunction approach allows the CPUID instruction to return a detailedpicture of the processor implementation and its capabilities—more detailed information than could bereturned by a single function. This flexibility also allows for the addition of new CPUID functions infuture processor generations.Function codes are loaded into the EAX register before executing the CPUID instruction. CPUIDfunctions are divided into two types:••Standard functions return information about features common to all x86 implementations,including the earliest features offered in the x86 architecture, as well as information about thepresence of newer features such as SSE, SSE2, and SSE3 instructions.Extended functions return information about AMD-specific features, such as the AMD extensionsto the MMX™ and 3DNow!™ instructions, and long mode.System Resources61AMD64 Technology24593—Rev.
3.13—July 2007See “CPUID” in Volume 3 for details on the operation of this instruction, and the AMD CPUIDSpecification (order# 25481) for information returned by each processor implementation.62System Resources24593—Rev. 3.13—July 20074AMD64 TechnologySegmented Virtual MemoryThe legacy x86 architecture supports a segment-translation mechanism that allows system software torelocate and isolate instructions and data anywhere in the virtual-memory space. A segment is acontiguous block of memory within the linear address space.
The size and location of a segment withinthe linear address space is arbitrary. Instructions and data can be assigned to one or more memorysegments, each with its own protection characteristics. The processor hardware enforces the rulesdictating whether one segment can access another segment.The segmentation mechanism provides ten segment registers, each of which defines a single segment.Six of these registers (CS, DS, ES, FS, GS, and SS) define user segments. User segments holdsoftware, data, and the stack and can be used by both application software and system software. Theremaining four segment registers (GDT, LDT, IDT, and TR) define system segments.
System segmentscontain data structures initialized and used only by system software. Segment registers contain a baseaddress pointing to the starting location of a segment, a limit defining the segment size, and attributesdefining the segment-protection characteristics.Although segmentation provides a great deal of flexibility in relocating and protecting software anddata, it is often more efficient to handle memory isolation and relocation with a combination ofsoftware and hardware paging support. For this reason, most modern system software bypasses thesegmentation features.
However, segmentation cannot be completely disabled, and an understandingof the segmentation mechanism is important to implementing long-mode system software.In long mode, the effects of segmentation depend on whether the processor is running in compatibilitymode or 64-bit mode:••In compatibility mode, segmentation functions just as it does in legacy mode, using legacy 16-bitor 32-bit protected mode semantics.64-bit mode, segmentation is disabled, creating a flat 64-bit virtual-address space. As will be seen,certain functions of some segment registers, particularly the system-segment registers, continue tobe used in 64-bit mode.4.1Real Mode SegmentationAfter reset or power-up, the processor always initially enters real mode.
Protected modes are enteredfrom real mode.As noted in “Real Addressing” on page 10, real mode (real-address mode), provides a physicalmemory space of 1 Mbyte. In this mode, a 20-bit physical address is determined by shifting a 16-bitsegment selector to the left four bits and adding the 16-bit effective address.Each 64K segment (CS, DS, ES, FS, GS, SS) is aligned on 16-byte boundaries. The segment base isthe lowest address in a given segment, and is equal to the segment selector * 16.
The POP and MOVinstructions can be used to load a (possibly) new segment selector into one of the segment registers.Segmented Virtual Memory63AMD64 Technology24593—Rev. 3.13—July 2007When this occurs, the selector is updated and the selector base is set to selector * 16. The segment limitand segment attributes are unchanged, but are normally 64K (the maximum allowable limit) andread/write data, respectively.On FAR transfers, CS (code segment) selector is updated to the new value, and the CS segment base isset to selector * 16. The CS segment limit and attributes are unchanged, but are usually 64K andread/write, respectively.If the interrupt descriptor table (IDT) is used to find the real mode IDT see “Real-Mode InterruptControl Transfers” on page 227.The GDT, LDT, and TSS (see below) are not used in real mode.4.2Virtual-8086 Mode SegmentationVirtual-8086 mode supports 16-bit real mode programs running under protected mode (see below).
Ituses a simple form of memory segmentation, optional paging, and limited protection checking.Programs running in virtual-8086 mode can access up to 1MB of memory space.As with real mode segmentation, each 64K segment (CS, DS, ES, FS, GS, SS) is aligned on 16-byteboundaries. The segment base is the lowest address in a given segment, and is equal to the segmentselector * 16.
The POP and MOV instructions work exactly as in real mode and can be used to load a(possibly) new segment selector into one of the segment registers. When this occurs, the selector isupdated and the selector base is set to selector * 16. The segment limit and segment attributes areunchanged, but are normally 64K (the maximum allowable limit) and read/write data, respectively.FAR transfers, with the exception of interrupts and exceptions, operate as in real mode. On FARtransfers, the CS (code segment) selector is updated to the new value, and the CS segment base is set toselector * 16.
The CS segment limit and attributes are unchanged, but are usually 64K and read/write,respectively. Interrupts and exceptions switch the processor to protected mode. (See Chapter 8,“Exceptions and Interrupts” for more information.)4.3Protected Mode Segmented-Memory ModelsSystem software can use the segmentation mechanism to support one of two basic segmented-memorymodels: a flat-memory model or a multi-segmented model. These segmentation models are supportedin legacy mode and in compatibility mode.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
