Volume 2 System Programming (794096), страница 25
Текст из файла (страница 25)
The model-specific registers supported by the AMD64architecture are introduced in this chapter.Because of their complexity, system-data structures are described in separate chapters. Refer to thefollowing chapters for detailed information on these data structures:•••Descriptors and descriptor tables are described in “Segmentation Data Structures and Registers”on page 65.Page-translation tables are described in “Legacy-Mode Page Translation” on page 120 and “LongMode Page Translation” on page 128.The task-state segment is described in “Legacy Task-State Segment” on page 311 and “64-Bit TaskState Segment” on page 315.Not all processor implementations are required to support all possible features. The last section in thischapter addresses processor-feature identification.
System software uses the capabilities described inthat section to determine which features are supported so that the appropriate service routines areloaded.3.1System-Control RegistersThe registers that control the AMD64 architecture operating environment include:••CR0—Provides operating-mode controls and some processor-feature controls.CR2—This register is used by the page-translation mechanism. It is loaded by the processor withthe page-fault virtual address when a page-fault exception occurs.•CR3—This register is also used by the page-translation mechanism.
It contains the base address ofthe highest-level page-translation table, and also contains cache controls for the specified table.CR4—This register contains additional controls for various operating-mode features.CR8—This new register, accessible in 64-bit mode using the REX prefix, is introduced by theAMD64 architecture. CR8 is used to prioritize external interrupts and is referred to as the taskpriority register (TPR).RFLAGS—This register contains processor-status and processor-control fields.
The status andcontrol fields are used primarily in the management of virtual-8086 mode, hardware multitasking,and interrupts.•••System Resources41AMD64 Technology•24593—Rev. 3.13—July 2007EFER—This model-specific register contains status and controls for additional features notmanaged by the CR0 and CR4 registers. Included in this register are the long-mode enable andactivation controls introduced by the AMD64 architecture.Control registers CR1, CR5–CR7, and CR9–CR15 are reserved.In legacy mode, all control registers and RFLAGS are 32 bits.
The EFER register is 64 bits in allmodes. The AMD64 architecture expands all 32-bit system-control registers to 64 bits. In 64-bit mode,the MOV CRn instructions read or write all 64 bits of these registers (operand-size prefixes areignored). In compatibility and legacy modes, control-register writes fill the low 32 bits with data andthe high 32 bits with zeros, and control-register reads return only the low 32 bits.In 64-bit mode, the high 32 bits of CR0 and CR4 are reserved and must be written with zeros. Writinga 1 to any of the high 32 bits results in a general-protection exception, #GP(0).
All 64 bits of CR2 arewritable. However, the MOV CRn instructions do not check that addresses written to CR2 are withinthe virtual-address limitations of the processor implementation.All CR3 bits are writable, except for unimplemented physical address bits, which must be cleared to 0.The upper 32 bits of RFLAGS are always read as zero by the processor. Attempts to load the upper 32bits of RFLAGS with anything other than zero are ignored by the processor.3.1.1 CR0 RegisterThe CR0 register is shown in Figure 3-1 on page 43. The legacy CR0 register is identical to the low 32bits of the register shown in Figure 3-1 on page 43 (CR0 bits 31–0).42System Resources24593—Rev.
3.13—July 2007AMD64 Technology6332Reserved, MBZ31 30 29 28P C NG D WBits63–3231302928–1918171615-654321019 18 17 16 15ReservedMnemonicReservedPGCDNWReservedAMReservedWPReservedNEETTSEMMPPEAWRMPDescriptionReserved, Must be ZeroPagingCache DisableNot WritethroughReservedAlignment MaskReservedWrite ProtectReservedNumeric ErrorExtension TypeTask SwitchedEmulationMonitor CoprocessorProtection EnabledFigure 3-1.6Reserved54N EE T3210T E M PS M P ER/WR/WR/WR/WR/WR/WR/WRR/WR/WR/WR/WControl Register 0 (CR0)The functions of the CR0 control bits are (unless otherwise noted, all bits are read/write):Protected-Mode Enable (PE) Bit. Bit 0. Software enables protected mode by setting PE to 1, anddisables protected mode by clearing PE to 0.
When the processor is running in protected mode,segment-protection mechanisms are enabled.See “Segment-Protection Overview” on page 93 for information on the segment-protectionmechanisms.Monitor Coprocessor (MP) Bit. Bit 1. Software uses the MP bit with the task-switched control bit(CR0.TS) to control whether execution of the WAIT/FWAIT instruction causes a device-not-availableexception (#NM) to occur, as follows:••If both the monitor-coprocessor and task-switched bits are set (CR0.MP=1 and CR0.TS=1), thenexecuting the WAIT/FWAIT instruction causes a device-not-available exception (#NM).If either the monitor-coprocessor or task-switched bits are clear (CR0.MP=0 or CR0.TS=0), thenexecuting the WAIT/FWAIT instruction proceeds normally.System Resources43AMD64 Technology24593—Rev.
3.13—July 2007Software typically should set MP to 1 if the processor implementation supports x87 instructions. Thisallows the CR0.TS bit to completely control when the x87-instruction context is saved as a result of atask switch.Emulate Coprocessor (EM) Bit. Bit 2. Software forces all x87 instructions to cause a device-not-available exception (#NM) by setting EM to 1. Likewise, setting EM to 1 forces an invalid-opcodeexception (#UD) when an attempt is made to execute any of the 64-bit or 128-bit media instructions.The exception handlers can emulate these instruction types if desired. Setting the EM bit to 1 does notcause an #NM exception when the WAIT/FWAIT instruction is executed.Task Switched (TS) Bit.
Bit 3. When an attempt is made to execute an x87 or media instruction whileTS=1, a device-not-available exception (#NM) occurs. Software can use this mechanism—sometimesreferred to as “lazy context-switching”—to save the unit contexts before executing the next instructionof those types. As a result, the x87 and media instruction-unit contexts are saved only when necessaryas a result of a task switch.When a hardware task switch occurs, TS is automatically set to 1. System software that implementssoftware task-switching rather than using the hardware task-switch mechanism can still use the TS bitto control x87 and media instruction-unit context saves.
In this case, the task-management softwareuses a MOV CR0 instruction to explicitly set the TS bit to 1 during a task switch. Software can clearthe TS bit by either executing the CLTS instruction or by writing to the CR0 register directly. Longmode system software can use this approach even though the hardware task-switch mechanism is notsupported in long mode.The CR0.MP bit controls whether the WAIT/FWAIT instruction causes an #NM exception whenTS=1.Extension Type (ET) Bit. Bit 4, read-only. In some early x86 processors, software set ET to 1 toindicate support of the 387DX math-coprocessor instruction set.
This bit is now reserved and forced to1 by the processor. Software cannot clear this bit to 0.Numeric Error (NE) Bit. Bit 5. Clearing the NE bit to 0 disables internal control of x87 floating-pointexceptions and enables external control. When NE is cleared to 0, the IGNNE# input signal controlswhether x87 floating-point exceptions are ignored:••When IGNNE# is 1, x87 floating-point exceptions are ignored.When IGNNE# is 0, x87 floating-point exceptions are reported by setting the FERR# input signalto 1. External logic can use the FERR# signal as an external interrupt.When NE is set to 1, internal control over x87 floating-point exception reporting is enabled and theexternal reporting mechanism is disabled.
It is recommended that software set NE to 1. This enablesoptimal performance in handling x87 floating-point exceptions.Write Protect (WP) Bit. Bit 16. Read-only pages are protected from supervisor-level writes when theWP bit is set to 1. When WP is cleared to 0, supervisor software can write into read-only pages.See “Page-Protection Checks” on page 141 for information on the page-protection mechanism.44System Resources24593—Rev. 3.13—July 2007AMD64 TechnologyAlignment Mask (AM) Bit. Bit 18. Software enables automatic alignment checking by setting theAM bit to 1 when eFLAGS.AC=1. Alignment checking can be disabled by clearing either AM oreFLAGS.AC to 0. When automatic alignment checking is enabled and CPL=3, a memory reference toan unaligned operand causes an alignment-check exception (#AC).Not Writethrough (NW) Bit.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
