Volume 2 System Programming (794096), страница 106
Текст из файла (страница 106)
These are legacy interrupts from legacy interrupt controller (PIC).7ExternalInterrupt is delivered to the INTR interrupt line of the core specified by the Destinationfield. These interrupts can be delivered even if the APIC is disabled.BhLINT1Deliver the interrupt to the INTR interrupt line of the CPU core specified by theDestination field. The vector and trigger mode are determined by the LINT1 LocalLVT Register.EhLINT0Deliver the interrupt to the INTR interrupt line of the CPU core specified by theDestination field.
The vector and trigger mode are determined by the LINT0 LocalLVT Register.Interrupt is delivered to the INTR interrupt line of the core operating at the lowestpriority of the cores specified by the logical ID of the Destination field.Interrupt is delivered to the STARTUP interrupt line of the core specified by theDestination field.For locally-generated interrupts, control is provided by local vector tables or LVTs. Separate LVTs areprovided for each interrupt source, allowing for unique entry point for each source. The LVT containsAdvanced Programmable Interrupt Controller (APIC)423AMD64 Technology24593—Rev. 3.13—July 2007the VECTOR[7:0], trigger mode and message type as well as other fields associated with the specificinterrupt.
The message type may be Fixed, SMI, NMI, or External interrupt. A Mask bit is alsoprovided to mask the interrupt.16.3Local APIC16.3.1 Local APIC EnableThe local APIC is controlled by the APIC enable bit (AE) in the APIC Base Address Register (MSR0000 001Bh). See Figure 16-2.When AE is set to 1, the local APIC is enabled and all interrupt types are accepted. When AE is clearedto 0, the local APIC is disabled, including all local vector table interrupts.Software can disable the local APIC, using the APIC_SW_EN bit in the Spurious Interrupt VectorRegister (APIC_F0). When this bit is cleared to zero, the local APIC is temporarily disabled:••••SMI, NMI, INIT, Startup, Remote Read, and LINT interrupts may be accepted.Pending interrupts in the ISR and IRR are held.Further fixed, lowest-priority, and ExtInt interrupts are not accepted.All LVT entry mask bits are set and cannot be cleared.6352 5132ABAReserved, MBZ(This is an architectural limit.
A given implementation may support fewer bits)3112 11 10 9AEABABits63-5251-121110-987-0MnemonicReservedABAAEReservedBSPReservedDescriptionReserved, Must be ZeroAPIC Base AddressAPIC EnableReserved, Must be ZeroBoot Strap ProcessorReserved, Must be ZeroRes,MBZ8BSP70Reserved, MBZR/WR/WR/WROFigure 16-2. APIC Base Address Register424Advanced Programmable Interrupt Controller (APIC)24593—Rev. 3.13—July 2007AMD64 TechnologyThe fields within the APIC Base Address register are as follows:•••Boot Strap CPU Core (BSP)—Bit 8. The BSC bit indicates this CPU core is the boot core of theBSP. Each CPU core that is not the boot core of the boot processor is an AP (ApplicationProcessor).APIC Enable (AE)—Bit 11.
This is the APIC enable bit. The local APIC is enabled and allinterruption types are accepted when AE is set to 1. Clearing AE to 0 disables the local APIC, andno local vector table interrupts are supported.APIC Base Address (ABA)—Bits 51-12. Specifies the base physical address for the APIC registerset. The address is extended by 12 bits at the least significant end to form a base address that isreset to a value of 0 FEE0 0000h.16.3.2 APIC RegistersThe local APIC is made up of APIC registers (see Table 16-3) and associated hardware used to controldelivery of interrupts to the associated CPU core interrupt handler. All APIC registers are memorymapped into the 4-Kbyte APIC register space, and are accessed with memory reads and writes.
Thememory address is indicated as:APIC Register address = APIC Base Address + Offsetwhere the APIC Base Address must point to an uncacheable memory region, and is located in APICBase Address Register, MSR 0000_001Bh. See Figure 16-2.Registers are aligned on 128-bit boundaries, and are normally 32 bits in length. Doubleword registersshould be accessed with doubleword loads and stores aligned on a 128-bit boundary.The state of the APIC registers after reset is provided in Table 16-3.Table 16-3.APIC RegistersOffsetNameReset20hAPIC ID Register??000000h30hAPIC Version Register80??0010h80hTask Priority Register (TPR)00000000h90hArbitration Priority Register (APR)00000000hA0hProcessor Priority Register (PPR)00000000hB0hEnd of Interrupt Register (EOI)C0hRemote Read Register00000000hD0hLogical Destination Register (LDR)00000000hE0hDestination Format Register (DFR)FFFFFFFFF0hSpurious Interrupt Vector Register000000FFh100-170hIn-Service Register (ISR)00000000h180-1F0hTrigger Mode Register (TMR)00000000hAdvanced Programmable Interrupt Controller (APIC)-425AMD64 TechnologyTable 16-3.24593—Rev.
3.13—July 2007APIC Registers (continued)OffsetNameReset200-270hInterrupt Request Register (IRR)00000000h280hError Status Register (ESR)00000000h300hInterrupt Command Register Low (bits 31:0)00000000h310hInterrupt Command Register High (bits 63:32)00000000h320hTimer Local Vector Table Entry00010000h330hThermal Local Vector Table Entry00010000h340hPerformance Counter Local Vector Table Entry00010000h350hLocal Interrupt 0 Vector Table Entry00010000h360hLocal Interrupt 1 Vector Table Entry00010000h370hError Vector Table Entry00010000h380hTimer Initial Count Register00000000h390hTimer Current Count Register00000000h3E0hTimer Divide Configuration Register00000000h400hExtended APIC Feature Register00040007h410hExtended APIC Control Register00000000h420hSpecific End of Interrupt Register (SEOI)00000000h480-4F0hInterrupt Enable Registers (IER)FFFFFFFFh500-530hExtended Interrupt [3:0] Local Vector Table Registers00000000h16.3.3 Local APIC IDUnique local APIC IDs are assigned to each CPU core in the system.
The value is determined byhardware, based on the number of CPU cores on the processor and the node ID of the processor.The APIC ID register is located in the APICID register at APIC offset=20h. See Figure 16-3. It ismodel dependent on whether software can modify the APIC ID Register. The initial value of theAPICID (after a reset) is the value returned in CPUID function 0000_0001h_EBX[31:24].3124 230AIDReserved, MBZBits Mnemonic Description31-24 AIDAPIC ID23-0 Reserved Reserved, Must be ZeroR/WR/WFigure 16-3. APIC ID Register (APIC Offset 20h)426Advanced<b>Текст обрезан, так как является слишком большим</b>.