Volume 2 System Programming (794096), страница 105
Текст из файла (страница 105)
Also undefined are ENTER when the processor is alreadyin SMM, and EXIT when the processor is not in SMM.418Secure Virtual Machine24593—Rev. 3.13—July 2007AMD64 Technology15.28.4 VM_HSAVE_PA MSR (C001_0117h)The 64-bit read/write VM_SAVE_PA MSR holds the physical address of a block of memory whereVMRUN saves host state, and from which #VMEXIT reloads host state.
The VMM software isexpected to set up this register before issuing the first VMRUN instruction. Software must not attemptto read or write the host save-state area directly.Writing this MSR causes a #GP if:••any of the low 12 bits of the address written are nonzero, orthe address written is greater than or equal to the maximum supported physical address for thisimplementation.15.29SVM-LockThe SVM-Lock feature allows software to prevent EFER.SVME from being set, eitherunconditionally or with a 64-bit key to re-enable SVM functionality.Support for SVM-Lock is indicated by EDX bit 2 as returned by CPUID function 8000_000Ah.
Onprocessors that support the SVM-Lock feature, SKINIT and STGI ignore EFER.SVME. Seedescriptions of LOCK and SVMDIS bits in Section 15.28.1, “VM_CR MSR (C001_0114h),” onpage 417. When the SVM-Lock feature is not available, hypervisors can use the read-onlyVM_CR.SVMDIS bit to detect SVM (see Section 15.4, “Enabling SVM,” on page 367).15.29.1 SVM_KEY MSR (C001_0118h)The write-only SVM_KEY MSR is used to create a password-protected mechanism to clearVM_CR.LOCK.When VM_CR.LOCK is zero, writes to SVM_KEY MSR set the 64-bit SVM Key value.When VM_CR.LOCK is one, writes to SVM_KEY MSR compare the written value to the SVM Keyvalue; if the values match and are non-zero, the VM_CR.LOCK bit is cleared.
If the values mismatchor the SVM Key value is zero, the write to SVM_KEY is ignored, and VM_CR.LOCK is unmodified.Software should read VM_CR.LOCK after writing SVM_KEY to determine whether the unlocksucceeded.If SVM Key is zero when VM_CR.LOCK is one, VM_CR.LOCK can only be cleared by a processorreset.To preserve the security of the SVM key, reading the SVM_KEY MSR always returns zero.15.30SMM-LockThe SMM-Lock feature allows software to prevent System Management Interrupts (SMI) from beingintercepted in SVM. The SmmLock bit is located in the HWCR MSR register.Secure Virtual Machine419AMD64 Technology24593—Rev. 3.13—July 200715.30.1 SMM_KEY MSR (C001_0119h)The write-only SMM_KEY MSR is used to create a password-protected mechanism to clearSmmLock.When SmmLock is zero, writes to SMM_KEY MSR set the 64-bit SMM Key value.When SmmLock is one, writes to SMM_KEY MSR compare the written value to the SMM Key value;if the values match and are non-zero, the SmmLock bit is cleared.
If the values mismatch or the SMMKey value is zero, the write to SMM_KEY is ignored, and SmmLock is unmodified. Software shouldread SmmLock after writing SMM_KEY to determine whether the unlock succeeded.If SMM_Key MSR is equal to zero when SmmLock is one, SmmLock can only be cleared by aprocessor reset.To preserve the security of the SMM key, reading SMM_KEY MSR always returns zero.15.30.2 SmmLock Bit — HWCR[0]The SmmLock bit (bit 0) is located in the HWCR MSR (C001_0015h). When SmmLock is clear, it canbe set to one. Once set, the bit cannot be cleared by software and writes to it are ignored. SmmLock canonly be cleared using the SMM_KEY MSR (see Section 15.30.1), or by a processor reset.
This bit isnot affected by INIT or SKINIT. When SmmLock is set, other SMM configuration registers cannot bewritten. See the model-specific BKDG for details. For complete information on the HWCR register,see the appropriate BIOS and kernal developer’s guide for your processor.)420Secure Virtual Machine24593—Rev. 3.13—July 200716AMD64 TechnologyAdvanced Programmable InterruptController (APIC)The Advanced Programmable Interrupt Controller (APIC) provides interrupt support on AMD64architecture processors.
The local APIC accepts interrupts from the system and delivers them to thelocal CPU core interrupt handler.Support for an enabled APIC feature is indicated by EDX bit 9 as returned by CPUID function0000_0001h.The APIC block diagram is provided in Figure 16-1.APIC TimerPerfMonCntrThermalSensorExtended IntrCPU#1CPUCoreCPU#2CPUCoreCPU#NCPUCoreInterruptHandlerInterruptHandlerInterruptHandlerAPIC TimerAPIC TimerLocalAPICPerfMonCntrLocalAPICPerfMonCntrThermalSensorThermalSensorExtended IntrExtended IntrAPIC ErrorAPIC ErrorLocalAPICAPIC ErrorInterrupt MessagesInterrupt MessagesI/O InterruptsIOAPICLegacyInterruptsPICMessageSignalledInterruptsFigure 16-1.
Block Diagram of a Typical APIC ImplementationAdvanced Programmable Interrupt Controller (APIC)421AMD64 Technology16.124593—Rev. 3.13—July 2007Sources of Interrupts to the Local APICEach CPU core has an associated local APIC which receives interrupts from the following sources:•••••I/O interrupts from the IOAPIC interrupt controller (including LINT0 and LINT1)Legacy interrupts (INTR and NMI) from the legacy interrupt controllerMessage Signalled InterruptsInterprocessor Interrupts (IPIs) from other local APICs.
Interprocessor Interrupts are used to sendinterrupts or to execute system wide functions between CPU cores in the system, including theoriginating CPU core (self-interrupt).Locally generated interrupts within the local APIC.
The local APIC receives local interrupts fromthe APIC timer, Performance Monitor Counters, thermal sensors, APIC errors and extendedinterrupts from implementation specific sources.The sources of interrupts for the local APIC are provided in Table 16-1.Table 16-1. Interrupt Sources for Local APICDescriptionMessage Type toLocal APICI/O interruptsSystem interrupts from I/O devices or system hardwarereceived through the I/O APIC and sent to the localAPIC as interrupt messages. They may be edgetriggered or level-sensitive.Fixed, Lowest Priority, SMI,NMI, INIT, Restart, Externalinterrupt, LINT0, LINT1Legacy InterruptsLegacy interrupts (INT and NMI) from the PIC and sentto the local APIC as interrupt messages.NMI, INTInterprocessor (IPI)Interprocessor interrupts.
Used for interrupt forwarding,system-wide functions, or software self-interrupts.Fixed, lowest priority, SMI,read request, NMI, INIT,Restart, External interruptAPIC TimerLocal interrupt from the programmed APIC timerreaches zero, under control of TIMER_LVT.Performance MonitorCounterLocal interrupt from the performance monitoring counterwhen it overflows, under control of PERF_CNT_LVT.Fixed, SMI, or NMIThermal SensorLocal interrupt from internal thermal sensors when ithas tripped, under control of THERMAL_LVT.Fixed, SMI, or NMIExtendedInterrupt[3:0]Local Interrupts from programmable internal CPU coresources, under the control of theEXTENDED_INTERRUPT[3:0]_LVT.Fixed, SMI, NMI, orExternal interruptAPIC Internal ErrorLocal interrupt when an error is detected within the localAPIC, under control of ERROR_LVT.Fixed, SMI, or NMISource422FixedAdvanced Programmable Interrupt Controller (APIC)24593—Rev.
3.13—July 200716.2AMD64 TechnologyInterrupt ControlI/O, legacy and interprocessor interrupts are sent via interrupt messages. The interrupt messagescontain the following information:••••Destination address of the local APIC.VECTOR[7:0] indicating interrupt priority of up to 256 interrupt vectors. This information iscaptured in the IRR register for Fixed and Lowest Priority interrupt message types.Trigger Mode indicating edge triggered or level-sensitive (which requires and EOI response to thesource).Message Type[3:0] indicating the type of interrupt to be presented to the local APIC.
For Fixed andLowest Priority message types, the interrupt is processed through the target local APIC. For allother message types, the interrupt is sent directly to the destination CPU core. There is a 5-lineinterrupt interface to the CPU core for INTR, SMI, NMI, INIT and STARTUP interrupts. Themessage types are provided in Table 16-2.Table 16-2. Message Type Field for Interrupt Messages to the Local APICMessageTypeNameDescription0FixedInterrupt is delivered to the INTR interrupt line of the core specified by the Destinationfield.1LowestPriority2SMIInterrupt is delivered to the SMI interrupt line of the core specified by the Destinationfield.3NMIInterrupt is delivered to the NMI interrupt line of the core specified by the Destinationfield. This is a nonmaskable interrupt, usually used for catastrophic errors.4INITInterrupts delivered to the INIT interrupt line of the core specified by the Destinationfield.5STARTUP6INTInterrupt is delivered to the INTR interrupt line of the core specified by the Destinationfield.
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