Volume 2 System Programming (794096), страница 28
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When an IRET is later executed toreturn to the instruction that caused the instruction-breakpoint #DB exception, the set RF bit (RF=1) isloaded from the interrupt-stack rFLAGS image. RF is not cleared by the processor until the instructioncausing the #DB exception successfully executes.Virtual-8086 Mode (VM) Bit. Bit 17. Software sets the VM bit to 1 to enable virtual-8086 mode.Software clears the VM bit to 0 to disable virtual-8086 mode.
System software can only change this bitusing a task switch or an IRET. It cannot modify the bit using the POPFD instruction.Alignment Check (AC) Bit. Bit 18. Software enables automatic alignment checking by setting theAC bit to 1 when CR0.AM=1. Alignment checking can be disabled by clearing either AC or CR0.AMto 0. When automatic alignment checking is enabled and the current privilege-level (CPL) is 3 (leastprivileged), a memory reference to an unaligned operand causes an alignment-check exception (#AC).Virtual Interrupt (VIF) Bit.
Bit 19. The VIF bit is a virtual image of the RFLAGS.IF bit. It is enabledwhen either virtual-8086 mode extensions are enabled (CR4.VME=1) or protected-mode virtualinterrupts are enabled (CR4.PVI=1), and the RFLAGS.IOPL field is less than 3. When enabled,instructions that ordinarily would modify the IF bit actually modify the VIF bit with no effect on theRFLAGS.IF bit.System software that supports virtual-8086 mode should enable the VIF bit using CR4.VME. Thisallows 8086 software to execute instructions that can set and clear the RFLAGS.IF bit without causingan exception.
With VIF enabled in virtual-8086 mode, those instructions set and clear the VIF bitinstead, giving the appearance to the 8086 software that it is modifying the RFLAGS.IF bit. Systemsoftware reads the VIF bit to determine whether or not to take the action desired by the 8086 software(enabling or disabling interrupts by setting or clearing the RFLAGS.IF bit).In long mode, the use of the VIF bit is supported when CR4.PVI=1. See “Virtual Interrupts” onpage 245 for more information on virtual interrupts.Virtual Interrupt Pending (VIP) Bit.
Bit 20. The VIP bit is provided as an extension to both virtual-8086 mode and protected mode. It is used by system software to indicate that an external, maskableinterrupt is pending (awaiting) execution by either a virtual-8086 mode or protected-mode interrupt-System Resources53AMD64 Technology24593—Rev. 3.13—July 2007service routine. Software must enable virtual-8086 mode extensions (CR4.VME=1) or protectedmode virtual interrupts (CR4.PVI=1) before using VIP.VIP is normally set to 1 by a protected-mode interrupt-service routine that was entered from virtual8086 mode as a result of an external, maskable interrupt.
Before returning to the virtual-8086 modeapplication, the service routine sets VIP to 1 if EFLAGS.VIF=1. When the virtual-8086 modeapplication attempts to enable interrupts by clearing EFLAGS.VIF to 0 while VIP=1, a generalprotection exception (#GP) occurs. The #GP service routine can then decide whether to allow thevirtual-8086 mode service routine to handle the pending external, maskable interrupt. (EFLAGS isspecifically referred to in this case because virtual-8086 mode is supported only from legacy mode.)In long mode, the use of the VIP bit is supported when CR4.PVI=1. See “Virtual Interrupts” onpage 245 for more information on virtual-8086 mode interrupts and the VIP bit.Processor Feature Identification (ID) Bit. Bit 21.
The ability of software to modify this bitindicates that the processor implementation supports the CPUID instruction. See “Processor FeatureIdentification” on page 61 for more information on the CPUID instruction.3.1.8 Extended Feature Enable Register (EFER)The extended-feature-enable register (EFER) contains control bits that enable additional processorfeatures not controlled by the legacy control registers. The EFER is a model-specific register (MSR)with an address of C000_0080h (see “Model-Specific Registers (MSRs)” on page 56 for moreinformation on MSRs). It can be read and written only by privileged software.
Figure 3-9 shows theformat of the EFER register.54System Resources24593—Rev. 3.13—July 2007AMD64 Technology6332Reserved, MBZ3115 14 13 12 11 10 9FFXSRReserved, MBZBits63–151413121110987-10MnemonicReserved, MBZFFXSRReserved, MBZSVMENXELMAReserved, MBZLMEReserved, RAZSCEDescriptionReserved, Must be ZeroFast FXSAVE/FXRSTORReserved, Must be ZeroSecure Virtual Machine EnableNo-Execute EnableLong Mode ActiveReserved, Must be ZeroLong Mode EnableReserved, Read as ZeroSystem Call ExtensionsFigure 3-9.8SMN L M LVBX M B MMZE A Z EE71Reserved, RAZ0SCER/WR/WR/WR/WRR/WR/WExtended Feature Enable Register (EFER)The function of the EFER bits are (unless otherwise noted, all bits are read/write):System-Call Extension (SCE) Bit.
Bit 0. Setting this bit to 1 enables the SYSCALL and SYSRETinstructions. Application software can use these instructions for low-latency system calls and returnsin a non-segmented (flat) address space. See “Fast System Call and Return” on page 147 for additionalinformation.Long Mode Enable (LME) Bit. Bit 8. Setting this bit to 1 enables the processor to activate long mode.Long mode is not activated until software enables paging some time later. When paging is enabledafter LME is set to 1, the processor sets the EFER.LMA bit to 1, indicating that long mode is not onlyenabled but also active. See Chapter 14, “Processor Initialization and Long Mode Activation,” formore information on activating long mode.Long Mode Active (LMA) Bit. Bit 10, read-only.
This bit indicates that long mode is active. Theprocessor sets LMA to 1 when both long mode and paging have been enabled by system software. SeeChapter 14, “Processor Initialization and Long Mode Activation,” for more information on activatinglong mode.When LMA=1, the processor is running either in compatibility mode or 64-bit mode, depending on thevalue of the L bit in a code-segment descriptor, as shown in Figure 1-6 on page 12.System Resources55AMD64 Technology24593—Rev.
3.13—July 2007When LMA=0, the processor is running in legacy mode. In this mode, the processor behaves like astandard 32-bit x86 processor, with none of the new 64-bit features enabled.No-Execute Enable (NXE) Bit. Bit 11. Setting this bit to 1 enables the no-execute page-protectionfeature. The feature is disabled when this bit is cleared to 0. See “No Execute (NX) Bit” on page 141for more information.Before setting NXE, system software should verify the processor supports the feature by examiningthe extended-feature flags returned by the CPUID instruction. For more information, see the AMDCPUID Specification, order# 25481.Secure Virtual Machine Enable (SVME) Bit. Bit 12. Enables the SVM extensions. When this bit iszero, the SVM instructions cause #UD exceptions. EFER.SVME defaults to a reset value of zero. Theeffect of turning off EFER.SVME while a guest is running is undefined; therefore, the VMM shouldalways prevent guests from writing EFER.
SVM extensions can be disabled by settingVM_CR.SVME_DISABLE. For more information, see descriptions of LOCK and SMVE_DISABLEbits in Section 15.28.1, “VM_CR MSR (C001_0114h),” on page 417.Fast FXSAVE/FXRSTOR (FFXSR) Bit. Bit 14. Setting this bit to 1 enables the FXSAVE andFXRSTOR instructions to execute faster in 64-bit mode at CPL 0. This is accomplished by not savingor restoring the XMM registers (XMM0-XMM15).
The FFXSR bit has no effect when theFXSAVE/FXRSTOR instructions are executed in non 64-bit mode, or when CPL > 0. The FFXSR bitdoes not affect the save/restore of the legacy x87 floating-point state, or the save/restore of MXCSR.Before setting FFXSR, system software should verify whether this feature is supported by examiningthe CPUID extended feature flags returned by the CPUID instruction. For more information, see"Function 8000_0001h: Processor Signature and AMD Features" in Volume 3.3.2Model-Specific Registers (MSRs)Processor implementations provide model-specific registers (MSRs) for software control over theunique features supported by that implementation.
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