Volume 2 System Programming (794096), страница 29
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Software reads and writes MSRs using theprivileged RDMSR and WRMSR instructions. Implementations of the AMD64 architecture cancontain a mixture of two basic MSR types:••Legacy MSRs. The AMD family of processors often share model-specific features with other x86processor implementations. Where possible, AMD implementations use the same MSRs for thesame functions. For example, the memory-typing and debug-extension MSRs are implemented onmany AMD and non-AMD processors.AMD model-specific MSRs.
There are many MSRs common to the AMD family of processors butnot to legacy x86 processors. Where possible, AMD implementations use the same AMD-specificMSRs for the same functions.Every model-specific register, as the name implies, is not necessarily implemented by all members ofthe AMD family of processors. Appendix A, “MSR Cross-Reference,” lists MSR-address rangescurrently used by various AMD and other x86 processors.56System Resources24593—Rev. 3.13—July 2007AMD64 TechnologyThe AMD64 architecture includes a number of features that are controlled using MSRs.
Those MSRsare shown in Figure 3-10 on page 57. The EFER register—described in “Extended Feature EnableRegister (EFER)” on page 54—is also an MSR.System-Configuration RegisterMemory-Typing RegistersSYSCFGMTRRcapMTRRdefTypeSystem-Linkage RegistersMTRRphysBasenSTARMTRRphysMasknLSTARMTRRfixnCSTARPATSFMASKTOP_MEMFS.baseTOP_MEM2GS.baseKernelGSbasePerformance-Monitoring RegistersSYSENTER_CSTSCSYSENTER_ESPPerfEvtSelnSYSENTER_EIPPerfCtrnDebug-Extension RegistersMachine-Check RegistersDebugCtlMSRMCG_CAPLastBranchFromIPMCG_STATLastBranchToIPMCG_CTLLastIntFromIPMCi_CTLLastIntToIPMCi_STATUSMCi_ADDRMCi_MISC513-262.epsFigure 3-10.AMD64 Architecture Model-Specific RegistersThe following sections briefly describe the MSRs in the AMD64 architecture.3.2.1 System Configuration Register (SYSCFG)The system-configuration register (SYSCFG) contains control bits for enabling and configuringsystem bus features.
SYSCFG is a model-specific register (MSR) with an address of C001_0010h.Figure 3-11 on page 58 shows the format of the SYSCFG register. Some features are implementationSystem Resources57AMD64 Technology24593—Rev. 3.13—July 2007specific, and are described in the BIOS writer’s guide for the implementation.
Implementation-specificfeatures are not shown in Figure 3-11 on page 58.31ReservedBits31-222120191817-0MnemonicReservedTOM2MVDMMFDMMFDEReserved22 21TOM220MVDM19MFDM18 17MFDE0ReservedDescriptionR/WMtrrTom2EnMtrrVarDramEnMtrrFixDramModEnMtrrFixDramEnR/WR/WR/WR/WFigure 3-11.System-Configuration Register (SYSCFG)The function of the SYSCFG bits are (all bits are read/write unless otherwise noted):MtrrFixDramEn Bit. Bit 18. Setting this bit to 1 enables use of the RdMem and WrMem attributes inthe fixed-range MTRR registers. When cleared, these attributes are disabled.
The RdMem andWrMem attributes allow system software to define fixed-range IORRs using the fixed-range MTRRs.See “Extended Fixed-Range MTRR Type-Field Encodings” on page 195 for information on using thisfeature.MtrrFixDramModEn Bit. Bit 19. Setting this bit to 1 allows software to read and write the RdMemand WrMem bits. When cleared, writes do not modify the RdMem and WrMem bits, and reads return0.
See “Extended Fixed-Range MTRR Type-Field Encodings” on page 195 for information on usingthis feature.MtrrVarDramEn Bit. Bit 20. Setting this bit to 1 enables the TOP_MEM register and the variable-range IORRs. These registers are disabled when the bit is cleared to 0. See “IORRs” on page 197 and“Top of Memory” on page 199 for information on using these features.MtrrTom2En Bit. Bit 21. Setting this bit to 1 enables the TOP_MEM2 register.
The register isdisabled when this bit is cleared to 0. See “Top of Memory” on page 199 for information on using thisfeature.3.2.2 System-Linkage RegistersSystem-linkage MSRs are used by system software to allow fast control transfers between applicationsand the operating system. The functions of these registers are:58System Resources24593—Rev. 3.13—July 2007AMD64 TechnologySTAR, LSTAR, CSTAR, and SFMASK Registers. These registers are used to provide mode-dependent linkage information for the SYSCALL and SYSRET instructions. STAR is used in legacymodes, LSTAR in 64-bit mode, and CSTAR in compatibility mode.
SFMASK is used by theSYSCALL instruction for rFLAGS in long mode.FS.base and GS.base Registers. These registers allow 64-bit base-address values to be specifiedfor the FS and GS segments, for use in 64-bit mode. See “FS and GS Registers in 64-Bit Mode” onpage 70 for a description of the special treatment the FS and GS segments receive.KernelGSbase Register. This register is used by the SWAPGS instruction. This instructionexchanges the value located in KernelGSbase with the value located in GS.base.SYSENTERx Registers.
The SYSENTER_CS, SYSENTER_ESP, and SYSENTER_EIP registersare used to provide linkage information for the SYSENTER and SYSEXIT instructions. Theseinstructions are only used in legacy mode.The system-linkage instructions and their use of MSRs are described in “Fast System Call and Return”on page 147.3.2.3 Memory-Typing RegistersMemory-typing MSRs are used to characterize, or type, memory. Memory typing allows software tocontrol the cacheability of memory, and determine how accesses to memory are ordered. The memorytyping registers perform the following functions:MTRRcap Register.
This register contains information describing the level of MTRR supportprovided by the processor.MTRRdefType Register. This register establishes the default memory type to be used for physicalmemory that is not specifically characterized using the fixed-range and variable-range MTRRs.MTRRphysBasen and MTRRphysMaskn Registers. These registers form a register pair that canbe used to characterize any address range within the physical-memory space, including all of physicalmemory.
Up to eight address ranges of varying sizes can be characterized using these registers.MTRRfixn Registers. These registers are used to characterize fixed-size memory ranges in the first 1Mbytes of physical-memory space.PAT Register. This register allows memory-type characterization based on the virtual (linear)address. It is an extension to the PCD and PWT memory types supported by the legacy pagingmechanism. The PAT mechanism provides the same memory-typing capabilities as the MTRRs, butwith the added flexibility provided by the paging mechanism.TOP_MEM and TOP_MEM2 Registers.
These top-of-memory registers allow system software tospecify physical addresses ranges as memory-mapped I/O locations.Refer to “Memory-Type Range Registers” on page 181 for more information on using these registers.System Resources59AMD64 Technology24593—Rev. 3.13—July 20073.2.4 Debug-Extension RegistersThe debug-extension MSRs provide software-debug capability not available in the legacy debugregisters (DR0–DR7). These MSRs allow single stepping and recording of control transfers to takeplace. The debug-extension registers perform the following functions:DebugCtlMSR Register. This register provides control over control-transfer recording and singlestepping, and external-breakpoint reporting and trace messages.LastBranchx and LastExceptionx Registers. T h e f o u r r e g i s t e r s , L a s t B r a n c h To I P,LastBranchFromIP, LastExceptionToIP, and LastExceptionFromIP, are all used to record the sourceand target of control transfers when branch recording is enabled.Refer to “Control-Transfer Breakpoint Features” on page 338 for more information on using thesedebug registers.3.2.5 Performance-Monitoring RegistersThe time-stamp counter and performance-monitoring registers are useful in identifying performancebottlenecks.
There can be any number of performance counters, each numbered from 0 to n. Theseregisters perform the following functions:TSC Register. This register is used to count processor-clock cycles. It can be read using the RDMSRinstruction, or it can be read using the either of the read time-stamp counter instructions, RDTSC orRDTSCP. System software can make RDTSC or RDTSCP available for use by non-privilegedsoftware by clearing the time-stamp disable bit (CR4.TSD) to 0.PerfEvtSeln Registers. These registers are used to specify the events counted by the correspondingperformance counter, and to control other aspects of its operation.PerfCtrn Registers.
These registers are performance counters that hold a count of processor eventsor the duration of events, under the control of the corresponding PerfEvtSeln register. Each PerfCtrnregister can be read using the RDMSR instruction, or they can be read using the read performancemonitor counter instruction, RDPMC. System software can make RDPMC available for use by nonprivileged software by setting the performance-monitor counter enable bit (CR4.PCE) to 1.Refer to “Using Performance Counters” on page 344 for more information on using these registers.3.2.6 Machine-Check RegistersThe machine-check registers control the detection and reporting of hardware machine-check errors.The types of errors that can be reported include cache-access errors, load-data and store-data errors,bus-parity errors, and ECC errors.
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