Volume 2 System Programming (794096), страница 33
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Global and Local Descriptor-Table Access4.6.2 Global Descriptor-Table RegisterThe global descriptor-table register (GDTR) points to the location of the GDT in memory and definesits size. This register is loaded from memory using the LGDT instruction (see “LGDT and LIDTInstructions” on page 153). Figure 4-7 shows the format of the GDTR in legacy mode andcompatibility mode.16-Bit Descriptor-Table Limit32-Bit Descriptor-Table Base Address513-220.epsFigure 4-7.GDTR and IDTR Format—Legacy ModesFigure 4-8 on page 73 shows the format of the GDTR in 64-bit mode.72Segmented Virtual Memory24593—Rev.
3.13—July 2007AMD64 Technology16-Bit Descriptor-Table Limit64-Bit Descriptor-Table Base Address513-266.epsFigure 4-8. GDTR and IDTR Format—Long ModeThe GDTR contains two fields:Limit. 2 bytes. These bits define the 16-bit limit, or size, of the GDT in bytes. The limit value is addedto the base address to yield the ending byte address of the GDT. A general-protection exception (#GP)occurs if software attempts to access a descriptor beyond the GDT limit.The offsets into the descriptor tables are not extended by the AMD64 architecture in support of longmode.
Therefore, the GDTR and IDTR limit-field sizes are unchanged from the legacy sizes. Theprocessor does check the limits in long mode during GDT and IDT accesses.Base Address. 8 bytes. The base-address field holds the starting byte address of the GDT in virtual-memory space. The GDT can be located at any byte address in virtual memory, but system softwareshould align the GDT on a doubleword boundary to avoid the potential performance penaltiesassociated with accessing unaligned data.The AMD64 architecture increases the base-address field of the GDTR to 64 bits so that systemsoftware running in long mode can locate the GDT anywhere in the 64-bit virtual-address space.
Theprocessor ignores the high-order 4 bytes of base address when running in legacy mode.4.6.3 Local Descriptor TableProtected-mode system software can optionally create a local descriptor table (LDT) to hold segmentdescriptors belonging to a single task or even multiple tasks. The LDT typically contains codesegment and data-segment descriptors as well as gate descriptors referenced by the specified task. Likethe GDT, system software can store the LDT anywhere in memory and should protect the segmentcontaining the LDT from non-privileged software.Segment selectors point to the LDT when the table-index bit (TI) in the selector is set to 1.
The selectorindex portion of the segment selector references a specific entry in the LDT (see Figure 4-6 onpage 72). Unlike the GDT, however, a selector index of 0 references the first entry in the LDT (whenTI=1, the selector is not a null selector).LDTs are described by system-segment descriptor entries located in the GDT, and a GDT can containmultiple LDT descriptors. The LDT system-segment descriptor defines the location, size, andprivilege rights for the LDT. Figure 4-9 on page 74 shows the relationship between the LDT and GDTdata structures.Segmented Virtual Memory73AMD64 Technology24593—Rev. 3.13—July 2007Loading a null selector into the LDTR is useful if software does not use an LDT.
This causes a #GP ifan erroneous reference is made to the LDT.GlobalDescriptorTableLocalDescriptorTableLDT SelectorLDT AttributesLDT LimitGDT LimitLDT Base AddressGDT Base AddressGlobal Descriptor Table RegisterFigure 4-9.Local Descriptor Table Register513-208.epsRelationship between the LDT and GDT4.6.4 Local Descriptor-Table RegisterThe local descriptor-table register (LDTR) points to the location of the LDT in memory, defines itssize, and specifies its attributes. The LDTR has two portions. A visible portion holds the LDT selector,and a hidden portion holds the LDT descriptor. When the LDT selector is loaded into the LDTR, theprocessor automatically loads the LDT descriptor from the GDT into the hidden portion of the LDTR.The LDTR is loaded in one of two ways:••Using the LLDT instruction (see “LLDT and LTR Instructions” on page 153).Performing a task switch (see “Switching Tasks” on page 319).Figure 4-10 on page 75 shows the format of the LDTR in legacy mode.74Segmented Virtual Memory24593—Rev.
3.13—July 2007AMD64 TechnologySelectorDescriptor Attributes32-Bit Descriptor-Table Limit32-Bit Descriptor-Table Base AddressHidden From SoftwareFigure 4-10.513-221.epsLDTR Format—Legacy ModeFigure 4-11 shows the format of the LDTR in long mode (both compatibility mode and 64-bit mode).SelectorDescriptor Attributes32-Bit Descriptor-Table Limit64-Bit Descriptor-Table Base AddressHidden From SoftwareFigure 4-11.513-267.epsLDTR Format—Long ModeThe LDTR contains four fields:LDT Selector. 2 bytes.
These bits are loaded explicitly from the TSS during a task switch, or by usingthe LLDT instruction. The LDT selector must point to an LDT system-segment descriptor entry in theGDT. If it does not, a general-protection exception (#GP) occurs.The following three fields are loaded automatically from the LDT descriptor in the GDT as a result ofloading the LDT selector.
The register fields are shown as shaded boxes in Figures 4-10 andFigure 4-11 on page 75.Base Address. The base-address field holds the starting byte address of the LDT in virtual-memoryspace. Like the GDT, the LDT can be located anywhere in system memory, but software should alignthe LDT on a doubleword boundary to avoid performance penalties associated with accessingunaligned data.Segmented Virtual Memory75AMD64 Technology24593—Rev. 3.13—July 2007The AMD64 architecture expands the base-address field of the LDTR to 64 bits so that systemsoftware running in long mode can locate an LDT anywhere in the 64-bit virtual-address space. Theprocessor ignores the high-order 32 base-address bits when running in legacy mode. Because theLDTR is loaded from the GDT, the system-segment descriptor format (LDTs are system segments) hasbeen expanded by the AMD64 architecture in support of 64-bit mode.
See “Long Mode DescriptorSummary” on page 92 for more information on this expanded format. The high-order base-address bitsare only loaded from 64-bit mode using the LLDT instruction (see “LLDT and LTR Instructions” onpage 153 for more information on this instruction).Limit. This field defines the limit, or size, of the LDT in bytes. The LDT limit as stored in the LDTRis 32 bits.
When the LDT limit is loaded from the GDT descriptor entry, the 20-bit limit field in thedescriptor is expanded to 32 bits and scaled based on the value of the descriptor granularity (G) bit. Fordetails on the limit biasing and granularity, see “Granularity (G) Bit” on page 79.If an attempt is made to access a descriptor beyond the LDT limit, a general-protection exception(#GP) occurs.The offsets into the descriptor tables are not extended by the AMD64 architecture in support of longmode.
Therefore, the LDTR limit-field size is unchanged from the legacy size. The processor doescheck the LDT limit in long mode during LDT accesses.Attributes. This field holds the descriptor attributes, such as privilege rights, segment presence andsegment granularity.4.6.5 Interrupt Descriptor TableThe final type of descriptor table is the interrupt descriptor table (IDT).
Multiple IDTs can bemaintained by system software. System software selects a specific IDT by loading the interruptdescriptor table register (IDTR) with a pointer to the IDT. As with the GDT and LDT, system softwarecan store the IDT anywhere in memory and should protect the segment containing the IDT from nonprivileged software.The IDT can contain only the following types of gate descriptors:•••Interrupt gatesTrap gatesTask gates.The use of gate descriptors by the interrupt mechanism is described in Chapter 8, “Exceptions andInterrupts.” A general-protection exception (#GP) occurs if the IDT descriptor referenced by aninterrupt or exception is not one of the types listed above.IDT entries are selected using the interrupt-vector number rather than a selector value.
The interruptvector number is scaled by the interrupt-descriptor entry size to form an offset into the IDT. Theinterrupt-descriptor entry size depends on the processor operating mode as follows:•76In long mode, interrupt descriptor-table entries are 16 bytes.Segmented Virtual Memory24593—Rev. 3.13—July 2007•AMD64 TechnologyIn legacy mode, interrupt descriptor-table entries are eight bytes.Figure 4-12 on page 77 shows how the interrupt-vector number indexes the IDT.InterruptDescriptor Table+Interrupt Vector+*Descriptor EntrySizeIDT Base AddressIDT LimitInterrupt Descriptor Table Register513-207.epsFigure 4-12. Indexing an IDT4.6.6 Interrupt Descriptor-Table RegisterThe interrupt descriptor-table register (IDTR) points to the IDT in memory and defines its size.
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