Volume 2 System Programming (794096), страница 35
Текст из файла (страница 35)
The accessed bit is set to 1 by the processor when the descriptor iscopied from the GDT or LDT into one of the data-segment registers or the stack-segment register. Thisbit is only cleared by software.Table 4-4 summarizes the data-segment type-field encodings.Table 4-4.Data-Segment Descriptor TypesType FieldBit 10Bit 9Bit 8ExpandDown(E)Writable(W)Accessed(A)0000Read-Only1001Read-Only — Accessed2010Read/Write011Read/Write — Accessed100Expand-down, Read-Only5101Expand-down, Read-Only — Accessed6110Expand-down, Read/Write7111Expand-down, Read/Write — AccessedHexValue3482Bit 11(Code/Data)0DescriptionSegmented Virtual Memory24593—Rev. 3.13—July 2007AMD64 TechnologyData-Segment Default Operand Size (D/B) Bit.
Bit 22 of byte +4. For expand-down data segments(E=1), setting D=1 sets the upper bound of the segment at 0_FFFF_FFFFh. Clearing D=0 sets theupper bound of the segment at 0_FFFFh.In the case where a data segment is referenced by the stack selector (SS), the D bit is referred to as theB bit. For stack segments, the B bit sets the default stack size.
Setting B=1 establishes a 32-bit stackreferenced by the 32-bit ESP register. Clearing B=0 establishes a 16-bit stack referenced by the 16-bitSP register.4.7.4 System DescriptorsThere are two general types of system descriptors: system-segment descriptors and gate descriptors.System-segment descriptors are used to describe the LDT and TSS segments. Gate descriptors do notdescribe segments, but instead hold pointers to code-segment descriptors. Gate descriptors are used forprotected-mode control transfers between less-privileged and more-privileged software.System-segment descriptors have the S bit cleared to 0.
The type field is used to differentiate thevarious LDT, TSS, and gate descriptors from one another. Table 4-5 summarizes the system-segmenttype-field encodings.Table 4-5.System-Segment Descriptor Types (S=0)—Legacy ModeHexValueType Field(Bits 11–8)00000Reserved (Illegal)10001Available 16-bit TSS20010LDT30011Busy 16-bit TSS4010016-bit Call Gate50101Task Gate6011016-bit Interrupt Gate7011116-bit Trap Gate81000Reserved (Illegal)91001Available 32-bit TSSA1010Reserved (Illegal)B1011Busy 32-bit TSSC110032-bit Call GateD1101Reserved (Illegal)E111032-bit Interrupt GateF111132-bit Trap GateSegmented Virtual MemoryDescription83AMD64 Technology24593—Rev. 3.13—July 2007Figure 4-16 shows the legacy-mode system-segment descriptor format used for referencing LDT andTSS segments (gray shading indicates the bit is reserved).
This format is also used in compatibilitymode. The system-segments are used as follows:••31The LDT typically holds segment descriptors belonging to a single task (see “Local DescriptorTable” on page 73).The TSS is a data structure for holding processor-state information. Processor state is saved in aTSS when a task is suspended, and state is restored from the TSS when a task is restarted. Systemsoftware must create at least one TSS referenced by the task register, TR. See “Legacy Task-StateSegment” on page 311 for more information on the TSS.24 23 22 21IBase Address 31–24GGNBase Address 15–0Figure 4-16.20 1916 15 14 13 12 11ASegmentVP DPL 0TypeLimit 19–16L870Base Address 23–16Segment Limit 15–0+4+0LDT and TSS Descriptor—Legacy/Compatibility Modes4.7.5 Gate DescriptorsGate descriptors hold pointers to code segments and are used to control access between code segmentswith different privilege levels.
There are four types of gate descriptors:•••84Call Gates—These gates (Figure 4-17 on page 85) are located in the GDT or LDT and are used tocontrol access between code segments in the same task or in different tasks. See “Control TransfersThrough Call Gates” on page 102 for information on how call gates are used to control accessbetween code segments operating in the same task. The format of a call-gate descriptor is shown inFigure 4-17 on page 85.Interrupt Gates and Trap Gates—These gates (Figure 4-18 on page 85) are located in the IDT andare used to control access to interrupt-service routines. “Legacy Protected-Mode Interrupt ControlTransfers” on page 229 contains information on using these gates for interrupt-control transfers.The format of interrupt-gate and trap-gate descriptors is shown in Figure 4-17 on page 85.Task Gates—These gates (Figure 4-19 on page 85) are used to control access between differenttasks.
They are also used to transfer control to interrupt-service routines if those routines arethemselves a separate task. See “Task-Management Resources” on page 306 for more informationon task gates and their use.Segmented Virtual Memory24593—Rev. 3.13—July 2007AMD64 Technology3116 15 14 13 12 11Target Code-Segment Offset 31–16PDPLTarget Code-Segment Selector0876540ReservedParameter CountIGNTypeTarget Code-Segment Offset 15–0+4+0Figure 4-17. Call-Gate Descriptor—Legacy Mode3116 15 14 13 12 11Target Code-Segment Offset 31–16PDPLTarget Code-Segment Selector087Type0Reserved, IGN+4Target Code-Segment Offset 15–0+0Figure 4-18.
Interrupt-Gate and Trap-Gate Descriptors—Legacy Mode3116 15 14 13 12 11Reserved, IGNTSS SelectorFigure 4-19.PDPL08Type70Reserved, IGNReserved, IGN+4+0Task-Gate Descriptor—Legacy ModeThere are several differences between the gate-descriptor format and the system-segment descriptorformat. These differences are described as follows, from least-significant to most-significant bitpositions:Target Code-Segment Offset. The 32-bit segment offset is formed by concatenating bits 31–16 ofbyte +4 with bits 15–0 of byte +0. The segment-offset field specifies the target-procedure entry point(offset) into the segment.
This field is loaded into the EIP register as a result of a control transfer usingthe gate descriptor.Target Code-Segment Selector. Bits 31–16 of byte +0. The segment-selector field identifies thetarget-procedure segment descriptor, located in either the GDT or LDT. The segment selector is loadedinto the CS segment register as a result of a control transfer using the gate descriptor.TSS Selector.
Bits 31–16 of byte +0 (task gates only). This field identifies the target-task TSSdescriptor, located in any of the three descriptor tables (GDT, LDT, and IDT).Segmented Virtual Memory85AMD64 Technology24593—Rev. 3.13—July 2007Parameter Count (Call Gates Only). Bits 4–0 of byte +4. Legacy-mode call-gate descriptorscontain a 5-bit parameter-count field.
This field specifies the number of parameters to be copied fromthe currently-executing program stack to the target program stack during an automatic stack switch.Automatic stack switches are performed by the processor during a control transfer through a call gateto a greater privilege-level. The parameter size depends on the call-gate size as specified in the typefield. 32-bit call gates copy 4-byte parameters, and 16-bit call gates copy 2-byte parameters. See“Stack Switching” on page 106 for more information on call-gate parameter copying.4.8Long-Mode Segment DescriptorsThe interpretation of descriptor fields is changed in long mode, and in some cases the format isexpanded. The changes depend on the operating mode (compatibility mode or 64-bit mode) and on thedescriptor type.
The following sections describe the changes.4.8.1 Code-Segment DescriptorsCode segments continue to exist in long mode. Code segments and their associated descriptors andselectors are needed to establish the processor operating mode as well as execution privilege-level. Thenew L attribute specifies whether the processor is running in compatibility mode or 64-bit mode (see“Long (L) Attribute Bit” on page 87). Figure 4-20 shows the long-mode code-segment descriptorformat.
In compatibility mode, the code-segment descriptor is interpreted and behaves just as it does inlegacy mode as described in “Code-Segment Descriptors” on page 80.In Figure 4-20, gray shading indicates the code-segment descriptor fields that are ignored in 64-bitmode when the descriptor is used during a memory reference. However, the fields are loaded wheneverthe segment register is loaded in 64-bit mode.3124 23 22 21 20 1916 15 14 13 12 11 10 9 8 70ASegmentBase Address 31–24G D L VBase Address 23–16P DPL 1 1 C R ALimit 19–16LBase Address 15–0Segment Limit 15–0+4+0Figure 4-20. Code-Segment Descriptor—Long ModeFields Ignored in 64-Bit Mode.
Segmentation is disabled in 64-bit mode, and code segments spanall of virtual memory. In this mode, code-segment base addresses are ignored. For the purpose ofvirtual-address calculations, the base address is treated as if it has a value of zero.Segment-limit checking is not performed, and both the segment-limit field and granularity (G) bit areignored.
Instead, the virtual address is checked to see if it is in canonical-address form.The readable (R) and accessed (A) attributes in the type field are also ignored.86Segmented Virtual Memory24593—Rev. 3.13—July 2007AMD64 TechnologyLong (L) Attribute Bit. Bit 21 of byte +4.
Long mode introduces a new attribute, the long (L) bit, incode-segment descriptors. This bit specifies that the processor is running in 64-bit mode (L=1) orcompatibility mode (L=0). When the processor is running in legacy mode, this bit is reserved.Compatibility mode, maintains binary compatibility with legacy 16-bit and 32-bit applications.Compatibility mode is selected on a code-segment basis, and it allows legacy applications to coexistunder the same 64-bit system software along with 64-bit applications running in 64-bit mode.
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