Volume 2 System Programming (794096), страница 36
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Systemsoftware running in long mode can execute existing 16-bit and 32-bit applications by clearing the L bitof the code-segment descriptor to 0.When L=0, the legacy meaning of the code-segment D bit (see “Code-Segment Default-Operand Size(D) Bit” on page 81)—and the address-size and operand-size prefixes—are observed. Segmentation isenabled when L=0. From an application viewpoint, the processor is in a legacy 16-bit or 32-bitoperating environment (depending on the D bit), even though long mode is activated.If the processor is running in 64-bit mode (L=1), the only valid setting of the D bit is 0.
This settingproduces a default operand size of 32 bits and a default address size of 64 bits. The combination L=1and D=1 is reserved for future use.“Instruction Prefixes” in Volume 3 describes the effect of the code-segment L and D bits on defaultoperand and address sizes when long mode is activated.
These default sizes can be overridden withoperand size, address size, and REX prefixes.4.8.2 Data-Segment DescriptorsData segments continue to exist in long mode. Figure 4-21 shows the long-mode data-segmentdescriptor format. In compatibility mode, data-segment descriptors are interpreted and behave just asthey do in legacy mode.In Figure 4-21, gray shading indicates the fields that are ignored in 64-bit mode when the descriptor isused during a memory reference.
However, the fields are loaded whenever the segment register isloaded in 64-bit mode.3124 23 22 21 20 1916 15 14 13 12 11 10 9 8 70DASegmentBase Address 31–24G /VBase Address 23–16P DPL 1 0 E W ALimit 19–16BLBase Address 15–0Segment Limit 15–0+4+0Figure 4-21. Data-Segment Descriptor—Long ModeFields Ignored in 64-Bit Mode. Segmentation is disabled in 64-bit mode.
The interpretation of thesegment-base address depends on the segment register used:Segmented Virtual Memory87AMD64 Technology24593—Rev. 3.13—July 2007In data-segment descriptors referenced by the DS, ES and SS segment registers, the base-addressfield is ignored. For the purpose of virtual-address calculations, the base address is treated as if ithas a value of zero.Data segments referenced by the FS and GS segment registers receive special treatment in 64-bitmode.
For these segments, the base address field is not ignored, and a non-zero value can be usedin virtual-address calculations. A 64-bit segment-base address can be specified using modelspecific registers. See “FS and GS Registers in 64-Bit Mode” on page 70 for more information.••Segment-limit checking is not performed on any data segments in 64-bit mode, and both the segmentlimit field and granularity (G) bit are ignored. The D/B bit is unused in 64-bit mode.The expand-down (E), writable (W), and accessed (A) type-field attributes are ignored.A data-segment-descriptor DPL field is ignored in 64-bit mode, and segment-privilege checks are notperformed on data segments.
System software can use the page-protection mechanisms to isolate andprotect data from unauthorized access.4.8.3 System DescriptorsIn long mode, the allowable system-descriptor types encoded by the type field are changed. Somedescriptor types are modified, and others are illegal.
The changes are summarized in Table 4-6. Anattempt to use an illegal descriptor type causes a general-protection exception (#GP).Table 4-6.System-Segment Descriptor Types—Long ModeType FieldHexValueBit 11Bit 10Bit 9Bit 800000100012001030011401005010160110701118100091001Available 64-bit TSSA1010Reserved (Illegal)B1011Busy 64-bit TSSC110064-bit Call GateDescriptionReserved (Illegal)64-bit LDT1Reserved (Illegal)Note:1. In 64-bit mode only. In compatibility mode, the type specifies a 32-bit LDT.88Segmented Virtual Memory24593—Rev. 3.13—July 2007Table 4-6.AMD64 TechnologySystem-Segment Descriptor Types—Long Mode (continued)Type FieldHexValueBit 11Bit 10Bit 9Bit 8D1101Reserved (Illegal)E111064-bit Interrupt GateF111164-bit Trap GateDescriptionNote:1.
In 64-bit mode only. In compatibility mode, the type specifies a 32-bit LDT.In long mode, the modified system-segment descriptor types are:•••The 32-bit LDT (02h), which is redefined as the 64-bit LDT.The available 32-bit TSS (09h), which is redefined as the available 64-bit TSS.The busy 32-bit TSS (0Bh), which is redefined as the busy 64-bit TSS.In 64-bit mode, the LDT and TSS system-segment descriptors are expanded by 64 bits, as shown inFigure 4-22 on page 89.
In this figure, gray shading indicates the fields that are ignored in 64-bit mode.Expanding the descriptors allows them to hold 64-bit base addresses, so their segments can be locatedanywhere in the virtual-address space. The expanded descriptor can be loaded into the correspondingdescriptor-table register (LDTR or TR) only from 64-bit mode. In compatibility mode, the legacysystem-segment descriptor format, shown in Figure 4-16 on page 84, is used.
See “LLDT and LTRInstructions” on page 153 for more information.312320 1916 15 14 13 12 11 10 9Reserved, IGN00008070Reserved, IGNBase Address 63–32Base Address 31–24GBase Address 15–0AVLSegmentLimit 19–16PDPL+12+80TypeBase Address 23–16Segment Limit 15–0+4+0Figure 4-22. System-Segment Descriptor—64-Bit ModeThe 64-bit system-segment base address must be in canonical form. Otherwise, a general-protectionexception occurs with a selector error-code, #GP(selector), when the system segment is loaded.System-segment limit values are checked by the processor in both 64-bit and compatibility modes,under the control of the granularity (G) bit.Figure 4-22 shows that bits 12–8 of dword +12 must be cleared to 0.
These bits correspond to the S andType fields in a legacy descriptor. Clearing these bits to 0 corresponds to an illegal type in legacy modeSegmented Virtual Memory89AMD64 Technology24593—Rev. 3.13—July 2007and causes a #GP if an attempt is made to access the upper half of a 64-bit mode system-segmentdescriptor as a legacy descriptor or as the lower half of a 64-bit mode system-segment descriptor.4.8.4 Gate DescriptorsAs shown in Table 4-6 on page 88, the allowable gate-descriptor types are changed in long mode.Some gate-descriptor types are modified and others are illegal. The modified gate-descriptor types inlong mode are:•••The 32-bit call gate (0Ch), which is redefined as the 64-bit call gate.The 32-bit interrupt gate (0Eh), which is redefined as the 64-bit interrupt gate.The 32-bit trap gate (0Fh), which is redefined as the 64-bit trap gate.In long mode, several gate-descriptor types are illegal.
An attempt to use these gates causes a generalprotection exception (#GP) to occur. The illegal gate types are:••••The 16-bit call gate (04h).The task gate (05h).The 16-bit interrupt gate (06h).The 16-bit trap gate (07h).In long mode, gate descriptors are expanded by 64 bits, allowing them to hold 64-bit offsets. The 64-bitcall-gate descriptor is shown in Figure 4-23 and the 64-bit interrupt gate and trap gate are shown inFigure 4-24 on page 91. In these figures, gray shading indicates the fields that are ignored in longmode.
The interrupt and trap gates contain an additional field, the IST, that is not present in the callgate—see “IST Field (Interrupt and Trap Gates)” on page 91.3116 15 14 13 12 11 10 9Reserved, IGN00008070Reserved, IGNTarget Offset 63–32Target Offset 31–16Target SelectorFigure 4-23.90PDPL+12+80TypeReserved, IGNTarget Offset 15–0+4+0Call-Gate Descriptor—Long ModeSegmented Virtual Memory24593—Rev. 3.13—July 200731AMD64 Technology16 15 14 13 12 11Target Offset 31–16Target SelectorFigure 4-24.87320Reserved, IGN+12Target Offset 63–32+8PDPL0TypeReserved, IGNISTTarget Offset 15–0+4+0Interrupt-Gate and Trap-Gate Descriptors—Long ModeThe target code segment referenced by a long-mode gate descriptor must be a 64-bit code segment(CS.L=1, CS.D=0).
If the target is not a 64-bit code segment, a general-protection exception,#GP(error), occurs. The error code reported depends on the gate type:••Call gates report the target code-segment selector as the error code.Interrupt and trap gates report the interrupt-vector number as the error code.A general-protection exception, #GP(0), occurs if software attempts to reference a long-mode gatedescriptor with a target-segment offset that is not in canonical form.It is possible for software to store legacy and long mode gate descriptors in the same descriptor table.Figure 4-23 on page 90 shows that bits 12–8 of byte +12 in a long-mode call gate must be cleared to 0.These bits correspond to the S and Type fields in a legacy call gate.
Clearing these bits to 0 correspondsto an illegal type in legacy mode and causes a #GP if an attempt is made to access the upper half of a64-bit mode call-gate descriptor as a legacy call-gate descriptor.It is not necessary to clear these same bits in a long-mode interrupt gate or trap gate. In long mode, theinterrupt-descriptor table (IDT) must contain 64-bit interrupt gates or trap gates. The processorautomatically indexes the IDT by scaling the interrupt vector by 16. This makes it impossible to accessthe upper half of a long-mode interrupt gate, or trap gate, as a legacy gate when the processor isrunning in long mode.IST Field (Interrupt and Trap Gates).
Bits 2–0 of byte +4. Long-mode interrupt gate and trap gatedescriptors contain a new, 3-bit interrupt-stack-table (IST) field not present in legacy gate descriptors.The IST field is used as an index into the IST portion of a long-mode TSS. If the IST field is not 0, theindex references an IST pointer in the TSS, which the processor loads into the RSP register when aninterrupt occurs. If the IST index is 0, the processor uses the legacy stack-switching mechanism (withsome modifications) when an interrupt occurs. See “Interrupt-Stack Table” on page 243 for moreinformation.Segmented Virtual Memory91AMD64 Technology24593—Rev. 3.13—July 2007Count Field (Call Gates).
The count field found in legacy call-gate descriptors is not supported inlong-mode call gates. In long mode, the field is reserved and should be cleared to zero.4.8.5 Long Mode Descriptor SummarySystem descriptors and gate descriptors are expanded by 64 bits to handle 64-bit base addresses in longmode or 64-bit mode. The mode in which the expansion occurs depends on the purpose served by thedescriptor, as follows:Expansion Only In 64-Bit Mode—The system descriptors and pseudo-descriptors that are loadedinto the GDTR, IDTR, LDTR, and TR registers are expanded only in 64-bit mode. They are notexpanded in compatibility mode.Expansion In Long Mode—Gate descriptors (call gates, interrupt gates, and trap gates) areexpanded in long mode (both 64-bit mode and compatibility mode).
Task gates and 16-bit gatedescriptors are illegal in long mode.••The AMD64 architecture redefines several of the descriptor-entry fields in support of long mode. Thespecific change depends on whether the processor is in 64-bit mode or compatibility mode. Table 4-7summarizes the changes in the descriptor entry field when the descriptor entry is loaded into a segmentregister (as opposed to when the segment register is subsequently used to access memory).Table 4-7.DescriptorFieldDescriptor-Entry Field Changes in Long ModeDescriptorTypeLong ModeCompatibility Mode64-Bit ModeCodeLimitDataOffsetGateSame as legacy x86Same as legacy x86Expanded to 64 bitsExpanded to 64 bitsSystemCodeBaseDataSame as legacy x86SystemSame as legacy x86SelectorGateSame as legacy x86IST1GateInterrupt and trap gates only. (New for long mode.)CodeDataS and TypeSame as legacy x86SystemTypes 02h, 09h, and 0Bh redefinedTypes 01h and 03h are illegalGateTypes 0Ch, 0Eh, and 0Fh redefinedTypes 04h–07h are illegalSame as legacy x86Note:1.
Not available (reserved) in legacy mode.92Segmented Virtual Memory24593—Rev. 3.13—July 2007Table 4-7.DescriptorFieldAMD64 TechnologyDescriptor-Entry Field Changes in Long Mode (continued)Long ModeDescriptorTypeCompatibility Mode64-Bit ModeCodeDataDPLSystemSame as legacy x86Same as legacy x86Same as legacy x86Same as legacy x86Same as legacy x86D=0 Indicates 64-bit address, 32-bit dataD=1 ReservedGateCodePresentDataSystemGateDefault SizeCodeData1LongCodeSame as legacy x86Specifies compatibility modeSpecifies 64-bit modeSame as legacy x86Same as legacy x86Same as legacy x86Same as legacy x86CodeGranularityDataSystemCodeAvailableDataSystemNote:1.
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