Volume 2 System Programming (794096), страница 34
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Thisregister is loaded from memory using the LIDT instruction (see “LGDT and LIDT Instructions” onpage 153). The format of the IDTR is identical to that of the GDTR in all modes. Figure 4-7 onpage 72 shows the format of the IDTR in legacy mode. Figure 4-8 on page 73 shows the format of theIDTR in long mode.The offsets into the descriptor tables are not extended by the AMD64 architecture in support of longmode. Therefore, the IDTR limit-field size is unchanged from the legacy size. The processor doescheck the IDT limit in long mode during IDT accesses.4.7Legacy Segment Descriptors4.7.1 Descriptor FormatSegment descriptors define, protect, and isolate segments from each other. There are two basic types ofdescriptors, each of which are used to describe different segment (or gate) types:•User Segments—These include code segments and data segments.
Stack segments are a type ofdata segment.Segmented Virtual Memory77AMD64 Technology•24593—Rev. 3.13—July 2007System Segments—System segments consist of LDT segments and task-state segments (TSS).Gate descriptors are another type of system-segment descriptor. Rather than describing segments,gate descriptors point to program entry points.Figure 4-13 shows the generic format for user-segment and system-segment descriptors. User andsystem segments are differentiated using the S bit. S=1 indicates a user segment, and S=0 indicates asystem segment. Gray shading indicates the field or bit is reserved.
The format for a gate descriptordiffers from the generic segment descriptor, and is described separately in “Gate Descriptors” onpage 84.3124 23 22 21 20 1916 15 14 13 12 11DASegment LimitBase Address 31–24G /VP DPL SType19–16BLBase Address 15–0870Base Address 23–16Segment Limit 15–0+4+0Figure 4-13. Generic Segment Descriptor—Legacy ModeFigure 4-13 shows the fields in a generic, legacy-mode, 8-byte segment descriptor.
In this figure, +0indicates the address of the descriptor’s first byte, and +4 indicates the address of the descriptor’s fifthbyte. The fields are defined as follows, from least-significant to most-significant bit positions:Segment Limit.
The 20-bit segment limit is formed by concatenating bits 19–16 of byte +4 with bits15–0 of byte +0. The segment limit defines the segment size, in bytes. The granularity (G) bit controlshow the segment-limit field is scaled (see “Granularity (G) Bit” on page 79). For data segments, theexpand-down (E) bit determines whether the segment limit defines the lower or upper segmentboundary (see “Expand-Down (E) Bit” on page 82).If software references a segment descriptor with an address beyond the segment limit, a generalprotection exception (#GP) occurs. The #GP occurs if any part of the memory reference falls outsidethe segment limit.
For example, a doubleword (4-byte) address reference causes a #GP if one or morebytes are located beyond the segment limit.Base Address. The 32-bit base address is formed by concatenating bits 31–24 of byte +4 with bits7–0 of byte +4, and with bits 15–0 of byte +0. The segment-base address field locates the start of asegment in virtual-address space.78Segmented Virtual Memory24593—Rev. 3.13—July 2007AMD64 TechnologyS Bit and Type Field. Bit 12 of byte +4, and bits 11–8 of byte +4.
The S and Type fields, together,specify the descriptor type and its access characteristics. Table 4-2 summarizes the descriptor types byS-field encoding and gives a cross reference to descriptions of the Type-field encodings.Table 4-2.S FieldDescriptor TypesDescriptorTypeType-Field EncodingLDT0 (System)TSSSee Table 4-5 on page 83Gate1 (User)CodeSee Table 4-3 on page 81DataSee Table 4-4 on page 82Descriptor Privilege-Level (DPL) Field.
Bits 14–13 of byte +4. The DPL field indicates thedescriptor-privilege level of the segment. DPL can be set to any value from 0 to 3, with 0 specifying themost privilege and 3 the least privilege. See “Data-Access Privilege Checks” on page 95 and “ControlTransfer Privilege Checks” on page 98 for more information on how the DPL is used during segmentprivilege-checks.Present (P) Bit.
Bit 15 of byte +4. The segment-present bit indicates that the segment referenced bythe descriptor is loaded in memory. If a reference is made to a descriptor entry when P=0, a segmentnot-present exception (#NP) occurs. This bit is set and cleared by system software and is never alteredby the processor.Available To Software (AVL) Bit. Bit 20 of byte +4. This field is available to software, which canwrite any value to it. The processor does not set or clear this field.Default Operand Size (D/B) Bit. Bit 22 of byte +4. The default operand-size bit is found in codesegment and data-segment descriptors but not in system-segment descriptors. Setting this bit to 1indicates a 32-bit default operand size, and clearing it to 0 indicates a 16-bit default size. The effect thisbit has on a segment depends on the segment-descriptor type.
See “Code-Segment Default-OperandSize (D) Bit” on page 81 for a description of the D bit in code-segment descriptors. “Data-SegmentDefault Operand Size (D/B) Bit” on page 83 describes the D bit in data-segment descriptors, includingstack segments, where the bit is referred to as the “B” bit.Granularity (G) Bit. Bit 23 of byte +4.
The granularity bit specifies how the segment-limit field isscaled. Clearing the G bit to 0 indicates that the limit field is not scaled. In this case, the limit equals thenumber of bytes available in the segment. Setting the G bit to 1 indicates that the limit field is scaled by4 Kbytes (4096 bytes). Here, the limit field equals the number of 4-Kbyte blocks available in thesegment.Setting a limit of 0 indicates a 1-byte segment limit when G = 0. Setting the same limit of 0 when G =1 indicates a segment limit of 4095.Segmented Virtual Memory79AMD64 Technology24593—Rev.
3.13—July 2007Reserved Bits. Generally, software should clear all reserved bits to 0, so they can be defined in futurerevisions to the AMD64 architecture.4.7.2 Code-Segment DescriptorsFigure 4-14 shows the code-segment descriptor format (gray shading indicates the bit is reserved). Allsoftware tasks require that a segment selector, referencing a valid code-segment descriptor, is loadedinto the CS register. Code segments establish the processor operating mode and execution privilegelevel. The segments generally contain only instructions and are execute-only, or execute and read-only.Software cannot write into a segment whose selector references a code-segment descriptor.3124 23 22 21 20 1916 15 14 13 12 11 10 9 8 70ASegmentBase Address 31–24G DVP DPL 1 1 C R ABase Address 23–16Limit 19–16LBase Address 15–0Figure 4-14.Segment Limit 15–0+4+0Code-Segment Descriptor—Legacy ModeCode-segment descriptors have the S bit set to 1, identifying the segments as user segments.
Type-fieldbit 11 differentiates code-segment descriptors (bit 11 set to 1) from data-segment descriptors (bit 11cleared to 0). The remaining type-field bits (10–8) define the access characteristics for the codesegment, as follows:Conforming (C) Bit. Bit 10 of byte +4. Setting this bit to 1 identifies the code segment as conforming.When control is transferred to a higher-privilege conforming code-segment (C=1) from a lowerprivilege code segment, the processor CPL does not change. Transfers to non-conforming codesegments (C=0) with a higher privilege-level than the CPL can occur only through gate descriptors.See “Control-Transfer Privilege Checks” on page 98 for more information on conforming and nonconforming code-segments.Readable (R) Bit.
Bit 9 of byte +4. Setting this bit to 1 indicates the code segment is both executableand readable as data. When this bit is cleared to 0, the code segment is executable, but attempts to readdata from the code segment cause a general-protection exception (#GP) to occur.Accessed (A) Bit. Bit 8 of byte +4. The accessed bit is set to 1 by the processor when the descriptor iscopied from the GDT or LDT into the CS register.
This bit is only cleared by software.Table 4-3 on page 81 summarizes the code-segment type-field encodings.80Segmented Virtual Memory24593—Rev. 3.13—July 2007Table 4-3.AMD64 TechnologyCode-Segment Descriptor TypesType FieldHexValueBit 10Bit 11(Code/Data) Conforming(C)Bit 9Bit 8Readable(R)Accessed(A)Description8000Execute-Only9001Execute-Only — AccessedA010Execute/ReadableB011Execute/Readable — Accessed100Conforming, Execute-OnlyD101Conforming, Execute-Only — AccessedE110Conforming, Execute/ReadableF111Conforming, Execute/Readable —AccessedC1Code-Segment Default-Operand Size (D) Bit.
Bit 22 of byte +4. In code-segment descriptors, theD bit selects the default operand size and address sizes. In legacy mode, when D=0 the default operandsize and address size is 16 bits and when D=1 the default operand size and address size is 32 bits.Instruction prefixes can be used to override the operand size or address size, or both.4.7.3 Data-Segment DescriptorsFigure 4-15 on page 81 shows the data-segment descriptor format.
Data segments contain nonexecutable information and can be accessed as read-only or read/write. They are referenced using theDS, ES, FS, GS, or SS data-segment registers. The DS data-segment register holds the segmentselector for the default data segment. The ES, FS and GS data-segment registers hold segmentselectors for additional data segments usable by the current software task.The stack segment is a special form of data-segment register. It is referenced using the SS segmentregister and must be read/write.
When loading the SS register, the processor requires that the selectorreference a valid, writable data-segment descriptor.3124 23 22 21 20 1916 15 14 13 12 11 10 9 8 70DASegmentBase Address 31–24G /VP DPL 1 0 E W ABase Address 23–16Limit 19–16BLBase Address 15–0Segment Limit 15–0+4+0Figure 4-15. Data-Segment Descriptor—Legacy ModeSegmented Virtual Memory81AMD64 Technology24593—Rev.
3.13—July 2007Data-segment descriptors have the S bit set to 1, identifying them as user segments. Type-field bit 11differentiates data-segment descriptors (bit 11 cleared to 0) from code-segment descriptors (bit 11 setto 1). The remaining type-field bits (10–8) define the data-segment access characteristics, as follows:Expand-Down (E) Bit. Bit 10 of byte +4. Setting this bit to 1 identifies the data segment as expand-down. In expand-down segments, the segment limit defines the lower segment boundary while thebase is the upper boundary.
Valid segment offsets in expand-down segments lie in the byte rangelimit+1 to FFFFh or FFFF_FFFFh, depending on the value of the data segment default operand size(D/B) bit.Expand-down segments are useful for stacks, which grow in the downward direction as elements arepushed onto the stack. The stack pointer, ESP, is decremented by an amount equal to the operand sizeas a result of executing a PUSH instruction.Clearing the E bit to 0 identifies the data segment as expand-up.
Valid segment offsets in expand-upsegments lie in the byte range 0 to segment limit.Writable (W) Bit. Bit 9 of byte +4. Setting this bit to 1 identifies the data segment as read/write. Whenthis bit is cleared to 0, the segment is read-only. A general-protection exception (#GP) occurs ifsoftware attempts to write into a data segment when W=0.Accessed (A) Bit. Bit 8 of byte +4.