Volume 2 System Programming (794096), страница 24
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The reassigned opcodes are used in 64-bit mode as REX instructionprefixes.x86 and AMD64 Architecture Differences35AMD64 TechnologyTable 2-5.24593—Rev. 3.13—July 2007Reassigned Instructions in 64-Bit ModeMnemonicARPLDEC and INCOpcode(hex)Description63Opcode for MOVSXD instruction in 64-bitmode. In all other modes, this the AdjustRequestor Privilege Level instruction opcode.40-4FDecrement by 1, Increment by 1. Two-byteversions of DEC and INC are still valid.2.5.11 FXSAVE and FXRSTOR InstructionsThe FXSAVE and FXRSTOR instructions are used to save and restore the entire 128-bit media, 64-bitmedia, and x87 instruction-set environment during a context switch. The AMD64 architecturemodifies the memory format used by these instructions in order to save and restore the full 64-bitinstruction and data pointers, as well as the XMM8–XMM15 registers.
Selection of the 32-bit legacyformat or the expanded 64-bit format is accomplished by using the corresponding operand size withthe FXSAVE and FXRSTOR instructions. When 64-bit software executes an FXSAVE and FXRSTORwith a 32-bit operand size (no operand-size override) the 32-bit legacy format is used. When 64-bitsoftware executes an FXSAVE and FXRSTOR with a 64-bit operand size, the 64-bit format is used.If the fast-FXSAVE/FXRSTOR (FFXSR) feature is enabled in EFER, FXSAVE and FXRSTOR do notsave or restore the XMM0-XMM15 registers when executed in 64-bit mode at CPL 0. The x87environment and MXCSR are saved whether fast-FXSAVE/FXRSTOR is enabled or not. Softwarecan use CPUID to determine whether the fast-FXSAVE/FXRSTOR feature is available (CPUIDfunction 8000_0001h, EDX bit 25).
The fast-FXSAVE/FXRSTOR feature has no effect onFXSAVE/FXRSTOR in non 64-bit mode or when CPL > 0.2.6Interrupts and ExceptionsWhen a processor is running in long mode, an interrupt or exception causes the processor to enter 64bit mode. All long-mode interrupt handlers must be implemented as 64-bit code. The AMD64architecture expands the legacy interrupt-processing and exception-processing mechanism to supporthandling of interrupts by 64-bit operating systems and applications. The changes are summarized inthe following sections. See “Long-Mode Interrupt Control Transfers” on page 239 for detailedinformation on these changes.2.6.1 Interrupt Descriptor TableThe long-mode interrupt-descriptor table (IDT) must contain 64-bit mode interrupt-gate or trap-gatedescriptors for all interrupts or exceptions that can occur while the processor is running in long mode.Task gates cannot be used in the long-mode IDT, because control transfers through task gates are notsupported in long mode.
In long mode, the IDT index is formed by scaling the interrupt vector by 16.In legacy protected mode, the IDT is indexed by scaling the interrupt vector by eight.36x86 and AMD64 Architecture Differences24593—Rev. 3.13—July 2007AMD64 Technology2.6.2 Stack Frame PushesIn legacy mode, the size of an IDT entry (16 bits or 32 bits) determines the size of interrupt-stackframe pushes, and SS:eSP is pushed only on a CPL change. In long mode, the size of interrupt stackframe pushes is fixed at eight bytes, because interrupts are handled in 64-bit mode. Long modeinterrupts also cause SS:RSP to be pushed unconditionally, rather than pushing only on a CPL change.2.6.3 Stack SwitchingLegacy mode provides a mechanism to automatically switch stack frames in response to an interrupt.In long mode, a slightly modified version of the legacy stack-switching mechanism is implemented,and an alternative stack-switching mechanism—called the interrupt stack table (IST)—is supported.Long-Mode Stack Switches.
When stacks are switched as part of a long-mode privilege-levelchange resulting from an interrupt, the following occurs:•••The target-stack pointer read from the TSS is a 64-bit RSP value.The SS register is loaded with a null selector.
Setting the new SS selector to null allows nestedcontrol transfers in 64-bit mode to be handled properly. The SS.RPL value is cleared to 0.The old SS and RSP are saved on the new stack.Interrupt Stack Table. In long mode, a new interrupt stack table (IST) mechanism is available as analternative to the modified legacy stack-switching mechanism. The IST mechanism unconditionallyswitches stacks when it is enabled. It can be enabled for individual interrupt vectors using a field in theIDT entry. This allows mixing interrupt vectors that use the modified legacy mechanism with vectorsthat use the IST mechanism. The IST pointers are stored in the long-mode TSS. The IST mechanism isonly available when long mode is enabled.2.6.4 IRET InstructionIn compatibility mode, IRET pops SS:eSP off the stack only if there is a CPL change.
This allowslegacy applications to run properly in compatibility mode when using the IRET instruction.In 64-bit mode, IRET unconditionally pops SS:eSP off of the interrupt stack frame, even if the CPLdoes not change. This is done because the original interrupt always pushes SS:RSP.
Because interruptstack-frame pushes are always eight bytes in long mode, an IRET from a long-mode interrupt handler(64-bit code) must pop eight-byte items off the stack. This is accomplished by preceding the IRETwith a 64-bit REX operand-size prefix.In long mode, an IRET can load a null SS selector from the stack under the following conditions:••The target operating mode is 64-bit mode.The target CPL<3.Allowing IRET to load SS with a null selector under these conditions makes it possible for theprocessor to unnest interrupts (and far CALLs) in long mode.x86 and AMD64 Architecture Differences37AMD64 Technology24593—Rev. 3.13—July 20072.6.5 Task-Priority Register (CR8)The AMD64 architecture allows software to define up to 15 external interrupt-priority classes.
Priorityclasses are numbered from 1 to 15, with priority-class 1 being the lowest and priority-class 15 thehighest.A new control register (CR8) is introduced by the AMD64 architecture for managing priority classes.This register, also called the task-priority register (TPR), uses the four low-order bits for specifying atask priority. How external interrupts are organized into these priority classes is implementationdependent. See “External Interrupt Priorities” on page 226 for information on this feature.2.6.6 New Exception ConditionsThe AMD64 architecture defines a number of new conditions that can cause an exception to occurwhen the processor is running in long mode. Many of the conditions occur when software attempts touse an address that is not in canonical form.
See “Vectors” on page 206 for information on the newexception conditions that can occur in long mode.2.7Hardware Task SwitchingThe legacy hardware task-switch mechanism is disabled when the processor is running in long mode.However, long mode requires system software to create data structures for a single task—the longmode task.•••TSS Descriptors—A new TSS-descriptor type, the 64-bit TSS type, is defined for use in longmode. It is the only valid TSS type that can be used in long mode, and it must be loaded into the TRby executing the LTR instruction in 64-bit mode. See “TSS Descriptor” on page 308 for additionalinformation.Task Gates—Because the legacy task-switch mechanism is not supported in long mode, softwarecannot use task gates in long mode. Any attempt to transfer control to another task through a taskgate causes a general-protection exception (#GP) to occur.Task-State Segment—A 64-bit task state segment (TSS) is defined for use in long mode.
This newTSS format contains 64-bit stack pointers (RSP) for privilege levels 0–2, interrupt-stack-table(IST) pointers, and the I/O-map base address. See “64-Bit Task State Segment” on page 315 foradditional information.2.8Long-Mode vs. Legacy-Mode DifferencesTable 2-6 on page 39 summarizes several major system-programming differences between 64-bitmode and legacy protected mode. The third column indicates whether the difference also applies tocompatibility mode. “Differences Between Long Mode and Legacy Mode” in Volume 3 summarizesthe application-programming model differences.38x86 and AMD64 Architecture Differences24593—Rev.
3.13—July 2007Table 2-6.AMD64 TechnologyDifferences Between Long Mode and Legacy ModeSubject64-Bit Mode DifferenceApplies ToCompatibilityMode?x86 ModesReal and virtual-8086 modes not supportedYesTask SwitchingTask switching not supportedYes64-bit virtual addressesNoAddressing4-level paging structuresPAE must always be enabledYesCS, DS, ES, SS segment bases are ignoredLoaded Segment (Usageduring memory reference)CS, DS, ES, FS, GS, SS segment limits are ignoredDS, ES, FS, GS attribute are ignoredNoCS, DS, ES, SS Segment prefixes are ignoredAll pushes are 8 bytesException and InterruptHandlingIDT entries are expanded to 16 bytesSS is not changed for stack switchYesSS:RSP is pushed unconditionallyAll pushes are 8 bytes16-bit call gates are illegalCall Gates32-bit call gate type is redefined as 64-bit call gate and isexpanded to 16 bytesYesSS is not changed for stack switchSystem-DescriptorRegistersSystem-Descriptor TableEntries and PseudoDescriptorsGDT, IDT, LDT, TR base registers expanded to 64 bitsYesLGDT and LIDT use expanded 10-byte pseudo-descriptorsLLDT and LTR use expanded 16-byte table entriesx86 and AMD64 Architecture DifferencesNo39AMD64 Technology4024593—Rev.
3.13—July 2007x86 and AMD64 Architecture Differences24593—Rev. 3.13—July 20073AMD64 TechnologySystem ResourcesThe operating system manages the software-execution environment and general system operationthrough the use of system resources. These resources consist of system registers (control registers andmodel-specific registers) and system-data structures (memory-management and protection tables).The system-control registers are described in detail in this chapter; many of the features they controlare described elsewhere in this volume.
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