Volume 2 System Programming (794096), страница 22
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LLDT and LTRinstructions can be used to load these descriptors into the LDTR and TR registers, respectively, from64-bit mode.In compatibility mode and legacy mode, the formats of the LDT and TSS system-segment descriptorsare unchanged. Also, unlike code-segment and data-segment descriptors, system-segment descriptorlimits are checked by the processor in long mode.Some legacy mode LDT and TSS type-field encodings are illegal in long mode (both compatibilitymode and 64-bit mode), and others are redefined to new types. See “System Descriptors” on page 88for additional information.Gate Descriptors. The following differences exist between gate descriptors in long mode (bothcompatibility mode and 64-bit mode) and in legacy mode:•••In long mode, all 32-bit gate descriptors are redefined as 64-bit gate descriptors, and are expandedto hold 64-bit offsets.
The length of a gate descriptor in long mode is therefore 128 bits (16 bytes),versus the 64 bits (8 bytes) in legacy mode.Some type-field encodings are illegal in long mode, and others are redefined to new types. See“Gate Descriptors” on page 90 for additional information.The interrupt-gate and trap-gate descriptors define a new field, called the interrupt-stack table(IST) field.2.3Protection ChecksThe AMD64 architecture makes the following changes to the protection mechanism in long mode:•••The page-protection-check mechanism is expanded in long mode to include the U/S and R/Wprotection bits stored in the PML4 entries and PDP entries.Several system-segment types and gate-descriptor types that are legal in legacy mode are illegal inlong mode (compatibility mode and 64-bit mode) and fail type checks when used in long mode.Segment-limit checks are disabled in 64-bit mode for the CS, DS, ES, FS, GS, and SS segments.Segment-limit checks remain enabled for the LDT, GDT, IDT and TSS system segments.All segment-limit checks are performed in compatibility mode.x86 and AMD64 Architecture Differences27AMD64 Technology•24593—Rev.
3.13—July 2007Code and data segments used in 64-bit mode are treated as both readable and writable.See “Page-Protection Checks” on page 141 and “Segment-Protection Overview” on page 93 fordetailed information on the protection-check changes.2.4RegistersThe AMD64 architecture adds additional registers to the architecture, and in many cases expands thesize of existing registers to 64 bits.
The 80-bit floating-point stack registers and their overlaid 64-bitMMX™ registers are not modified by the AMD64 architecture.2.4.1 General-Purpose RegistersIn 64-bit mode, the general-purpose registers (GPRs) are 64 bits wide, and eight additional GPRs areavailable. The GPRs are: RAX, RBX, RCX, RDX, RDI, RSI, RBP, RSP, and the new R8–R15registers. To access the full 64-bit operand size, or the new R8–R15 registers, an instruction mustinclude a new REX instruction-prefix byte (see “REX Prefixes” on page 29 for a summary of thisprefix).In compatibility and legacy modes, the GPRs consist only of the eight legacy 32-bit registers.
Alllegacy rules apply for determining operand size.2.4.2 128-Bit Media RegistersIn 64-bit mode, eight additional 128-bit XMM registers are available, XMM8–XMM15. A REXinstruction prefix is used to access these registers. In compatibility and legacy modes, the XMMregisters consist of the eight 128-bit legacy registers, XMM0–XMM7.2.4.3 Flags RegisterThe flags register is expanded to 64 bits, and is called RFLAGS. All 64 bits can be accessed in 64-bitmode, but the upper 32 bits are reserved and always read back as zeros. Compatibility mode and legacymode can read and write only the lower-32 bits of RFLAGS (the legacy EFLAGS).2.4.4 Instruction PointerIn long mode, the instruction pointer is extended to 64 bits, to support 64-bit code offsets.
This 64-bitinstruction pointer is called RIP.2.4.5 Stack PointerIn 64-bit mode, the size of the stack pointer, RSP, is always 64 bits. The stack size is not controlled bya bit in the SS descriptor, as it is in compatibility or legacy mode, nor can it be overridden by aninstruction prefix. Address-size overrides are ignored for implicit stack references.28x86 and AMD64 Architecture Differences24593—Rev. 3.13—July 2007AMD64 Technology2.4.6 Control RegistersThe AMD64 architecture defines several enhancements to the control registers (CRn).
In long mode,all control registers are expanded to 64 bits, although the entire 64 bits can be read and written onlyfrom 64-bit mode. A new control register, the task-priority register (CR8 or TPR) is added, and can beread and written from 64-bit mode. Last, the function of the page-enable bit (CR0.PG) is expanded.When long mode is enabled, the PG bit is used to activate and deactivate long mode.2.4.7 Debug RegistersIn long mode, all debug registers are expanded to 64 bits, although the entire 64 bits can be read andwritten only from 64-bit mode.
Expanded register encodings for the decode registers allow up to eightnew registers to be defined (DR8–DR15), although presently those registers are not supported by theAMD64 architecture.2.4.8 Extended Feature Register (EFER)The EFER is expanded by the AMD64 architecture to include a long-mode-enable bit (LME), and along-mode-active bit (LMA). These new bits can be accessed from legacy mode and long mode.2.4.9 Memory Type Range Registers (MTRRs)The legacy MTRRs are architecturally defined as 64 bits, and can accommodate the maximum 52-bitphysical address allowed by the AMD64 architecture. From both long mode and legacy mode,implementations of the AMD64 architecture reference the entire 52-bit physical-address value storedin the MTRRs. Long mode and legacy mode system software can update all 64 bits of the MTRRs tomanage the expanded physical-address space.2.4.10 Other Model-Specific Registers (MSRs)Several other MSRs have fields holding physical addresses.
Examples include the APIC-base registerand top-of-memory register. Generally, any model-specific register that contains a physical address isdefined architecturally to be 64 bits wide, and can accommodate the maximum physical-address sizedefined by the AMD64 architecture. When physical addresses are read from MSRs by the processor,the entire value is read regardless of the operating mode. In legacy implementations, the high-orderMSR bits are reserved, and software must write those values with zeros. In legacy mode on AMD64architecture implementations, software can read and write all supported high-order MSR bits.2.5Instruction Set2.5.1 REX PrefixesREX prefixes are a new family of instruction-prefix bytes used in 64-bit mode to:••Specify the new GPRs and XMM registers.Specify a 64-bit operand size.x86 and AMD64 Architecture Differences29AMD64 Technology••24593—Rev.
3.13—July 2007Specify additional control registers. One additional control register, CR8, is defined in 64-bitmode.Specify additional debug registers (although none are currently defined).Not all instructions require a REX prefix. The prefix is necessary only if an instruction references oneof the extended registers or uses a 64-bit operand. If a REX prefix is used when it has no meaning, it isignored.Default 64-Bit Operand Size. In 64-bit mode, two groups of instructions have a default operand sizeof 64 bits and thus do not need a REX prefix for this operand size:••Near branches.All instructions, except far branches, that implicitly reference the RSP. See “Instructions thatReference RSP” on page 31 for additional information.2.5.2 Segment-Override Prefixes in 64-Bit ModeIn 64-bit mode, the DS, ES, SS, and CS segment-override prefixes have no effect.
These four prefixesare no longer treated as segment-override prefixes in the context of multiple-prefix rules. Instead, theyare treated as null prefixes.The FS and GS segment-override prefixes are treated as segment-override prefixes in 64-bit mode. Useof the FS and GS prefixes cause their respective segment bases to be added to the effective addresscalculation.
See “FS and GS Registers in 64-Bit Mode” on page 70 for additional information on usingthese segment registers.2.5.3 Operands and ResultsThe AMD64 architecture provides support for using 64-bit operands and generating 64-bit resultswhen operating in 64-bit mode. See “Operands” in Volume 1 for details.Operand-Size Overrides. In 64-bit mode, the default operand size is 32 bits. A REX prefix can beused to specify a 64-bit operand size.
Software uses a legacy operand-size (66h) prefix to toggle to 16bit operand size. The REX prefix takes precedence over the legacy operand-size prefix.Zero Extension of Results. In 64-bit mode, when performing 32-bit operations with a GPRdestination, the processor zero-extends the 32-bit result into the full 64-bit destination. Both 8-bit and16-bit operations on GPRs preserve all unwritten upper bits of the destination GPR. This is consistentwith legacy 16-bit and 32-bit semantics for partial-width results.2.5.4 Address CalculationsThe AMD64 architecture modifies aspects of effective-address calculation to support 64-bit mode.These changes are summarized in the following sections. See “Memory Addressing” in Volume 1 fordetails.30x86 and AMD64 Architecture Differences24593—Rev.
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