Volume 2 System Programming (794096), страница 21
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3.13—July 20072AMD64 Technologyx86 and AMD64 Architecture DifferencesThe AMD64 architecture is designed to provide full binary compatibility with all previous AMDimplementations of the x86 architecture. This chapter summarizes the new features and architecturalenhancements introduced by the AMD64 architecture, and compares those features and enhancementswith previous AMD x86 processors. Most of the new capabilities introduced by the AMD64architecture are available only in long mode (64-bit mode, compatibility mode, or both).
However,some of the new capabilities are also available in legacy mode, and are mentioned where appropriate.The material throughout this chapter assumes the reader has a solid understanding of the x86architecture. For those who are unfamiliar with the x86 architecture, please read the remainder of thisvolume before reading this chapter.2.1Operating ModesSee “Operating Modes” on page 11 for a complete description of the operating modes supported by theAMD64 architecture.2.1.1 Long ModeThe AMD64 architecture introduces long mode and its two sub-modes: 64-bit mode and compatibilitymode.64-Bit Mode.
64-bit mode provides full support for 64-bit system software and applications. The newfeatures introduced in support of 64-bit mode are summarized throughout this chapter. To use 64-bitmode, a 64-bit operating system and tool chain are required.Compatibility Mode. Compatibility mode allows 64-bit operating systems to implement binarycompatibility with existing 16-bit and 32-bit x86 applications.
It allows these applications to run,without recompilation, under control of a 64-bit operating system in long mode. The architecturalenhancements introduced by the AMD64 architecture that support compatibility mode aresummarized throughout this chapter.Unsupported Modes. Long mode does not support the following two operating modes:••Virtual-8086 Mode—The virtual-8086 mode bit (EFLAGS.VM) is ignored when the processor isrunning in long mode. When long mode is enabled, any attempt to enable virtual-8086 mode issilently ignored. System software must leave long mode in order to use virtual-8086 mode.Real Mode—Real mode is not supported when the processor is operating in long mode becauselong mode requires that protected mode be enabled.2.1.2 Legacy ModeThe AMD64 architecture supports a pure x86 legacy mode, which preserves binary compatibility notonly with existing 16-bit and 32-bit applications but also with existing 16-bit and 32-bit operatingx86 and AMD64 Architecture Differences23AMD64 Technology24593—Rev.
3.13—July 2007systems. Legacy mode supports real mode, protected mode, and virtual-8086 mode. A reset alwaysplaces the processor in legacy mode (real mode), and the processor continues to run in legacy modeuntil system software activates long mode. New features added by the AMD64 architecture that aresupported in legacy mode are summarized in this chapter.2.1.3 System-Management ModeThe AMD64 architecture supports system-management mode (SMM). SMM can be entered from bothlong mode and legacy mode, and SMM can return directly to either mode. The following differencesexist between the support of SMM in the AMD64 architecture and the SMM support found in previousprocessor generations:•••••The SMRAM state-save area format is changed to hold the 64-bit processor state.
This state-savearea format is used regardless of whether SMM is entered from long mode or legacy mode.The auto-halt restart and I/O-instruction restart entries in the SMRAM state-save area are one byteinstead of two bytes.The initial processor state upon entering SMM is expanded to reflect the 64-bit nature of theprocessor.New conditions exist that can cause a processor shutdown while exiting SMM.SMRAM caching considerations are modified because the legacy FLUSH# external signal(writeback, if modified, and invalidate) is not supported on implementations of the AMD64architecture.See Chapter 10, “System-Management Mode,” for more information on the SMM differences.2.2Memory ModelThe AMD64 architecture provides enhancements to the legacy memory model to support very largephysical-memory and virtual-memory spaces while in long mode.
Some of this expanded support forphysical memory is available in legacy mode.2.2.1 Memory AddressingVirtual-Memory Addressing. Virtual-memory support is expanded to 64 address bits in long mode.This allows up to 16 exabytes of virtual-address space to be accessed. The virtual-address spacesupported in legacy mode is unchanged.Physical-Memory Addressing. Physical-memory support is expanded to 52 address bits in longmode and legacy mode.
This allows up to 4 petabytes of physical memory to be accessed. Theexpanded physical-memory support is achieved by using paging and the page-size extensions.Implementations can support fewer than 52 physical-address bits. The first implementation of theAMD64 architecture, for example, supports 40-bit physical addressing in both long mode and legacymode.24x86 and AMD64 Architecture Differences24593—Rev. 3.13—July 2007AMD64 TechnologyEffective Addressing. The effective-address length is expanded to 64 bits in long mode. Aneffective-address calculation uses 64-bit base and index registers, and sign-extends 8-bit and 32-bitdisplacements to 64 bits. In legacy mode, effective addresses remain 32 bits long.2.2.2 Page TranslationThe AMD64 architecture defines an expanded page-translation mechanism supporting translation of a64-bit virtual address to a 52-bit physical address.
See “Long-Mode Page Translation” on page 128 fordetailed information on the enhancements to page translation in the AMD64 architecture. Theenhancements are summarized below.Physical-Address Extensions (PAE). The AMD64 architecture requires physical-addressextensions to be enabled (CR4.PAE=1) before long mode is entered. When PAE is enabled, all pagingdata-structures are 64 bits, allowing references into the full 52-bit physical-address space supported bythe architecture.Page-Size Extensions (PSE). Page-size extensions (CR4.PSE) are ignored in long mode. Longmode does not support the 4-Mbyte page size enabled by page-size extensions. Long mode does,however, support 4-Kbyte and 2-Mbyte page sizes.Paging Data Structures.
The AMD64 architecture extends the page-translation data structures insupport of long mode. The extensions are:•••Page-map level-4 (PML4)—Long mode defines a new page-translation data structure, the PML4table. The PML4 table sits at the top of the page-translation hierarchy and references PDP tables.Page-directory pointer (PDP)—The PDP tables in long mode are expanded from 4 entries to 512entries each.Page-directory pointer entry (PDPE)—Previously undefined fields within the legacy-mode PDPEare defined by the AMD64 architecture.CR3 Register. The CR3 register is expanded to 64 bits for use in long-mode page translation.
Whenlong mode is active, the CR3 register references the base address of the PML4 table. In legacy mode,the upper 32 bits of CR3 are masked by the processor to support legacy page translation. CR3references the PDP base-address when physical-address extensions are enabled, or the page-directorytable base-address when physical-address extensions are disabled.Legacy-Mode Enhancements. Legacy-mode software can take advantage of the enhancementsmade to the physical-address extension (PAE) support and page-size extension (PSE) support. Thefour-level page translation mechanism introduced by long mode is not available to legacy-modesoftware.•PAE—When physical-address extensions are enabled (CR4.PAE=1), the AMD64 architectureallows legacy-mode software to load up to 52-bit (maximum size) physical addresses into the PDEand PTE. (Addresses are expanded to the maximum physical address size supported by theimplementation.)x86 and AMD64 Architecture Differences25AMD64 Technology•24593—Rev.
3.13—July 2007PSE—The use of page-size extensions allows legacy mode software to define 4-Mbyte pages usingthe 32-bit page-translation tables. When page-size extensions are enabled (CR4.PSE=1), theAMD64 architecture enhances the 4-Mbyte PDE to support 40 physical-address bits.See “Legacy-Mode Page Translation” on page 120 for more information on these enhancements.2.2.3 SegmentationIn long mode, the effects of segmentation depend on whether the processor is running in compatibilitymode or 64-bit mode:••In compatibility mode, segmentation functions just as it does in legacy mode, using legacy 16-bitor 32-bit protected mode semantics.64-bit mode requires a flat-memory model for creating a flat 64-bit virtual-address space.
Much ofthe segmentation capability present in legacy mode and compatibility mode is disabled when theprocessor is running in 64-bit mode.The differences in the segmentation model as defined by the AMD64 architecture are summarized inthe following sections. See Chapter 4, “Segmented Virtual Memory,” for a thorough description ofthese differences.Descriptor-Table Registers. In long mode, the base-address portion of the descriptor-table registers(GDTR, IDTR, LDTR, and TR) are expanded to 64 bits.
The full 64-bit base address can only beloaded by software when the processor is running in 64-bit mode (using the LGDT, LIDT, LLDT, andLTR instructions, respectively). However, the full 64-bit base address is used by a processor running incompatibility mode (in addition to 64-bit mode) when making a reference into a descriptor table.A processor running in legacy mode can only load the low 32 bits of the base address, and the high 32bits are ignored when references are made to the descriptor tables.Code-Segment Descriptors. The AMD64 architecture defines a new code-segment descriptorattribute, L (long). In compatibility mode, the processor treats code-segment descriptors as it does inlegacy mode, with the exception that the processor recognizes the L attribute.
If a code descriptor withL=1 is loaded in compatibility mode, the processor leaves compatibility mode and enters 64-bit mode.In legacy mode, the L attribute is reserved.The following differences exist for code-segment descriptors in 64-bit mode only:•••The CS base-address field is ignored by the processor.The CS limit field is ignored by the processor.Only the L (long), D (default size), and DPL (descriptor-privilege level) fields are used by theprocessor in 64-bit mode.
All remaining attributes are ignored.Data-Segment Descriptors. The following differences exist for data-segment descriptors in 64-bitmode only:•26The DS, ES, and SS descriptor base-address fields are ignored by the processor.x86 and AMD64 Architecture Differences24593—Rev. 3.13—July 2007••AMD64 TechnologyThe FS and GS descriptor base-address fields are expanded to 64 bits and used in effective-addresscalculations. The 64 bits of base address are mapped to model-specific registers (MSRs), and canonly be loaded using the WRMSR instruction.The limit fields and attribute fields of all data-segment descriptors (DS, ES, FS, GS, and SS) areignored by the processor.In compatibility mode, the processor treats data-segment descriptors as it does in legacy mode.Compatibility mode ignores the high 32 bits of base address in the FS and GS segment descriptorswhen calculating an effective address.System-Segment Descriptors. In 64-bit mode only, The LDT and TSS system-segment descriptorformats are expanded by 64 bits, allowing them to hold 64-bit base addresses.
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