Volume 2 System Programming (794096), страница 19
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3.13—July 2007AMD64 Technology1.3.5 System Management Mode (SMM)System management mode (SMM) is an operating mode designed for system-control activities that aretypically transparent to conventional system software. Power management is one popular use forsystem management mode. SMM is primarily targeted for use by the basic input-output system (BIOS)and specialized low-level device drivers. The code and data for SMM are stored in the SMM memoryarea, which is isolated from main memory by the SMM output signal.SMM is entered by way of a system management interrupt (SMI).
Upon recognizing an SMI, theprocessor enters SMM and switches to a separate address space where the SMM handler is located andexecutes. In SMM, the processor supports real-mode addressing with 4 Gbyte segment limits anddefault operand, address, and stack sizes of 16 bits (prefixes can be used to override these defaults).1.4System RegistersFigure 1-7 on page 16 shows the system registers defined for the AMD64 architecture. Systemsoftware uses these registers to, among other things, manage the processor operating environment,define system resource characteristics, and to monitor software execution. With the exception of theRFLAGS register, system registers can be read and written only from privileged software.Except for the descriptor-table registers and task register, the AMD64 architecture defines all systemregisters to be 64 bits wide.
The descriptor table and task registers are defined by the AMD64architecture to include 64-bit base-address fields, in addition to their other fields.As shown in Figure 1-7 on page 16, the system registers include:•••••Control Registers—These registers are used to control system operation and some system features.See “System-Control Registers” on page 41 for details.System-Flags Register—The RFLAGS register contains system-status flags and masks. It is alsoused to enable virtual-8086 mode and to control application access to I/O devices and interrupts.See “RFLAGS Register” on page 50 for details.Descriptor-Table Registers—These registers contain the location and size of descriptor tablesstored in memory. Descriptor tables hold segmentation data structures used in protected mode.
See“Descriptor Tables” on page 71 for details.Task Register—The task register contains the location and size in memory of the task-statesegment. The hardware-multitasking mechanism uses the task-state segment to hold stateinformation for a given task. The TSS also holds other data, such as the inner-level stack pointersused when changing to a higher privilege level. See “Task Register” on page 309 for details.Debug Registers—Debug registers are used to control the software-debug mechanism, and toreport information back to a debug utility or application.
See “Debug Registers” on page 326 fordetails.System-Programming Overview15AMD64 Technology24593—Rev. 3.13—July 2007Control RegistersExtended-Feature-Enable RegisterMemory-Typing RegistersCR0EFERMTRRcapCR2MTRRdefTypeCR3System-Configuration RegisterMTRRphysBasenCR4SYSCFGMTRRphysMasknMTRRfixnCR8System-Flags RegisterRFLAGSSystem-Linkage RegistersPATSTARTOP_MEMLSTARTOP_MEM2CSTARPerformance-Monitoring RegistersSFMASKDebug RegistersFS.baseTSCDR0GS.basePerfEvtSelnDR1KernelGSbasePerfCtrnDR2SYSENTER_CSDR3SYSENTER_ESPMachine-Check RegistersDR6SYSENTER_EIPMCG_CAPMCG_STATDR7MCG_CTLDebug-Extension RegistersDescriptor-Table RegistersGDTRIDTRLDTRMCi_CTLDebugCtlMSRMCi_STATUSLastBranchFromIPMCi_ADDRLastBranchToIPMCi_MISCLastIntFromIPLastIntToIPModel-Specific RegistersTask RegisterTR513-260.epsFigure 1-7.
System RegistersAlso defined as system registers are a number of model-specific registers included in the AMD64architectural definition, and shown in Figure 1-7:•16Extended-Feature-Enable Register—The EFER register is used to enable and report status onspecial features not controlled by the CRn control registers.
In particular, EFER is used to controlactivation of long mode. See “Extended Feature Enable Register (EFER)” on page 54 for moreinformation.System-Programming Overview24593—Rev. 3.13—July 2007••••••AMD64 TechnologySystem-Configuration Register—The SYSCFG register is used to enable and configure systembus features.
See “System Configuration Register (SYSCFG)” on page 57 for more information.System-Linkage Registers—These registers are used by system-linkage instructions to specifyoperating-system entry points, stack locations, and pointers into system-data structures. See “FastSystem Call and Return” on page 147 for details.Memory-Typing Registers—Memory-typing registers can be used to characterize (type) systemmemory. Typing memory gives system software control over how instructions and data are cached,and how memory reads and writes are ordered.
See “MTRRs” on page 182 for details.Debug-Extension Registers—These registers control additional software-debug reporting features.See “Debug Registers” on page 326 for details.Performance-Monitoring Registers—Performance-monitoring registers are used to countprocessor and system events, or the duration of events. See “Performance Optimization” onpage 339 for more information.Machine-Check Registers—The machine-check registers control the response of the processor tonon-recoverable failures.
They are also used to report information on such failures back to systemutilities designed to respond to such failures. See “Machine Check MSRs” on page 254 for moreinformation.1.5System-Data StructuresFigure 1-8 on page 18 shows the system-data structures defined for the AMD64 architecture. Systemdata structures are created and maintained by system software for use by the processor when runningin protected mode. A processor running in protected mode uses these data structures to managememory and protection, and to store program-state information when an interrupt or task switchoccurs.System-Programming Overview17AMD64 Technology24593—Rev. 3.13—July 2007Segment Descriptors (Contained in Descriptor Tables)CodeGateStackTask-State SegmentDataLocal-Descriptor TableTask-State SegmentDescriptor TablesGlobal-Descriptor TableInterrupt-Descriptor TableLocal-Descriptor TableDescriptorGate DescriptorDescriptorDescriptorGate DescriptorDescriptor.........DescriptorGate DescriptorDescriptorPage-Translation TablesPage-Map Level-4Page-Directory PointerPage DirectoryPage Table513-261.epsFigure 1-8.
System-Data StructuresAs shown in Figure 1-8, the system-data structures include:••18Descriptors—A descriptor provides information about a segment to the processor, such as itslocation, size and privilege level. A special type of descriptor, called a gate, is used to provide acode selector and entry point for a software routine.
Any number of descriptors can be defined, butsystem software must at a minimum create a descriptor for the currently executing code segmentand stack segment. See “Legacy Segment Descriptors” on page 77, and “Long-Mode SegmentDescriptors” on page 86 for complete information on descriptors.Descriptor Tables—As the name implies, descriptor tables hold descriptors. The global-descriptortable holds descriptors available to all programs, while a local-descriptor table holds descriptorsused by a single program. The interrupt-descriptor table holds only gate descriptors used bySystem-Programming Overview24593—Rev.
3.13—July 2007••AMD64 Technologyinterrupt handlers. System software must initialize the global-descriptor and interrupt-descriptortables, while use of the local-descriptor table is optional. See “Descriptor Tables” on page 71 formore information.Task-State Segment—The task-state segment is a special segment for holding processor-stateinformation for a specific program, or task. It also contains the stack pointers used when switchingto more-privileged programs. The hardware multitasking mechanism uses the state information inthe segment when suspending and resuming a task.
Calls and interrupts that switch stacks cause thestack pointers to be read from the task-state segment. System software must create at least onetask-state segment, even if hardware multitasking is not used. See “Legacy Task-State Segment”on page 311, and “64-Bit Task State Segment” on page 315 for details.Page-Translation Tables—Use of page translation is optional in protected mode, but it is requiredin long mode. A four-level page-translation data structure is provided to allow long-modeoperating systems to translate a 64-bit virtual-address space into a 52-bit physical-address space.Legacy protected mode can use two- or three-level page-translation data structures.
See “PageTranslation Overview” on page 115 for more information on page translation.1.6InterruptsThe AMD64 architecture provides a mechanism for the processor to automatically suspend (interrupt)software execution and transfer control to an interrupt handler when an interrupt or exception occurs.An interrupt handler is privileged software designed to identify and respond to the cause of an interruptor exception, and return control back to the interrupted software.
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