Volume 2 System Programming (794096), страница 16
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Hennessy and David A. Patterson, Computer Architecture, Morgan Kaufmann Publishers,San Mateo, CA, 1996.Thom Hogan, The Programmer’s PC Sourcebook, Microsoft Press, Redmond, WA, 1991.••••••••••••••••••xlHal Katircioglu, Inside the 486, Pentium, and Pentium Pro, Peer-to-Peer Communications, MenloPark, CA, 1997.IBM Corporation, 486SLC Microprocessor Data Sheet, IBM Corporation, Essex Junction, VT,1993.IBM Corporation, 486SLC2 Microprocessor Data Sheet, IBM Corporation, Essex Junction, VT,1993.IBM Corporation, 80486DX2 Processor Floating Point Instructions, IBM Corporation, EssexJunction, VT, 1995.IBM Corporation, 80486DX2 Processor BIOS Writer's Guide, IBM Corporation, Essex Junction,VT, 1995.IBM Corporation, Blue Lightning 486DX2 Data Book, IBM Corporation, Essex Junction, VT,1994.Institute of Electrical and Electronics Engineers, IEEE Standard for Binary Floating-PointArithmetic, ANSI/IEEE Std 754-1985.Institute of Electrical and Electronics Engineers, IEEE Standard for Radix-Independent FloatingPoint Arithmetic, ANSI/IEEE Std 854-1987.Muhammad Ali Mazidi and Janice Gillispie Mazidi, 80X86 IBM PC and Compatible Computers,Prentice-Hall, Englewood Cliffs, NJ, 1997.Hans-Peter Messmer, The Indispensable Pentium Book, Addison-Wesley, New York, 1995.Karen Miller, An Assembly Language Introduction to Computer Architecture: Using the IntelPentium, Oxford University Press, New York, 1999.Stephen Morse, Eric Isaacson, and Douglas Albert, The 80386/387 Architecture, John Wiley &Sons, New York, 1987.NexGen Inc., Nx586TM Processor Data Book, NexGen Inc., Milpitas, CA, 1993.NexGen Inc., Nx686TM Processor Data Book, NexGen Inc., Milpitas, CA, 1994.Preface24593—Rev.
3.13—July 2007•••••••••••AMD64 TechnologyBipin Patwardhan, Introduction to the Streaming SIMD Extensions in the Pentium® III,www.x86.org/articles/sse_pt1/ simd1.htm, June, 2000.Peter Norton, Peter Aitken, and Richard Wilton, PC Programmer’s Bible, Microsoft Press,Redmond, WA, 1993.PharLap 386|ASM Reference Manual, Pharlap, Cambridge MA, 1993.PharLap TNT DOS-Extender Reference Manual, Pharlap, Cambridge MA, 1995.Sen-Cuo Ro and Sheau-Chuen Her, i386/i486 Advanced Programming, Van Nostrand Reinhold,New York, 1993.Jeffrey P. Royer, Introduction to Protected Mode Programming, course materials for an onsiteclass, 1992.Tom Shanley, Protected Mode System Architecture, Addison Wesley, NY, 1996.SGS-Thomson Corporation, 80486DX Processor SMM Programming Manual, SGS-ThomsonCorporation, 1995.Walter A. Triebel, The 80386DX Microprocessor, Prentice-Hall, Englewood Cliffs, NJ, 1992.John Wharton, The Complete x86, MicroDesign Resources, Sebastopol, California, 1994.Web sites and newsgroups:- www.amd.com- news.comp.arch- news.comp.lang.asm.x86- news.intel.microprocessors- news.microsoftPrefacexliAMD64 Technologyxlii24593—Rev.
3.13—July 2007Preface24593—Rev. 3.13—July 20071AMD64 TechnologySystem-Programming OverviewThis entire volume is intended for system-software developers—programmers writing operatingsystems, loaders, linkers, device drivers, or utilities that require access to system resources. Thesesystem resources are generally available only to software running at the highest-privilege level(CPL=0), also referred to as privileged software. Privilege levels and their interactions are fullydescribed in “Segment-Protection Overview” on page 93.This chapter introduces the basic features and capabilities of the AMD64 architecture that are availableto system-software developers.
The concepts include:••The supported address forms and how memory is organized.How memory-management hardware makes use of the various address forms to access memory.•The processor operating modes, and how the memory-management hardware supports each ofthose modes.The system-control registers used to manage system resources.The interrupt and exception mechanism, and how it is used to interrupt program execution and toreport errors.Additional, miscellaneous features available to system software, including support for hardwaremultitasking, reporting machine-check exceptions, debugging software problems, and optimizingsoftware performance.•••Many of the legacy features and capabilities are enhanced by the AMD64 architecture to support 64bit operating systems and applications, while providing backward-compatibility with existingsoftware.1.1Memory ModelThe AMD64 architecture memory model is designed to allow system software to manage applicationsoftware and associated data in a secure fashion.
The memory model is backward-compatible with thelegacy memory model. Hardware-translation mechanisms are provided to map addresses betweenvirtual-memory space and physical-memory space. The translation mechanisms allow systemsoftware to relocate applications and data transparently, either anywhere in physical-memory space, orin areas on the system hard drive managed by the operating system.In long mode, the AMD64 architecture implements a flat-memory model. In legacy mode, thearchitecture implements all legacy memory models.System-Programming Overview1AMD64 Technology24593—Rev. 3.13—July 20071.1.1 Memory AddressingThe AMD64 architecture supports address relocation.
To do this, several types of addresses are neededto completely describe memory organization. Specifically, four types of addresses are defined by theAMD64 architecture:••••Logical addressesEffective addresses, or segment offsets, which are a portion of the logical address.Linear (virtual) addressesPhysical addressesLogical Addresses. A logical address is a reference into a segmented-address space.
It is comprisedof the segment selector and the effective address. Notationally, a logical address is represented asLogical Address = Segment Selector : OffsetThe segment selector specifies an entry in either the global or local descriptor table. The specifieddescriptor-table entry describes the segment location in virtual-address space, its size, and othercharacteristics. The effective address is used as an offset into the segment specified by the selector.Logical addresses are often referred to as far pointers. Far pointers are used in software addressingwhen the segment reference must be explicit (i.e., a reference to a segment outside the currentsegment).Effective Addresses. The offset into a memory segment is referred to as an effective address (see“Segmentation” on page 5 for a description of segmented memory).
Effective addresses are formed byadding together elements comprising a base value, a scaled-index value, and a displacement value. Theeffective-address computation is represented by the equationEffective Address = Base + (Scale x Index) + DisplacementThe elements of an effective-address computation are defined as follows:••••Base—A value stored in any general-purpose register.Scale—A positive value of 1, 2, 4, or 8.Index—A two’s-complement value stored in any general-purpose register.Displacement—An 8-bit, 16-bit, or 32-bit two’s-complement value encoded as part of theinstruction.Effective addresses are often referred to as near pointers. A near pointer is used when the segmentselector is known implicitly or when the flat-memory model is used.Long mode defines a 64-bit effective-address length.
If a processor implementation does not supportthe full 64-bit virtual-address space, the effective address must be in canonical form (see “CanonicalAddress Form” on page 4).2System-Programming Overview24593—Rev. 3.13—July 2007AMD64 TechnologyLinear (Virtual) Addresses. The segment-selector portion of a logical address specifies a segment-descriptor entry in either the global or local descriptor table. The specified segment-descriptor entrycontains the segment-base address, which is the starting location of the segment in linear-addressspace.
A linear address is formed by adding the segment-base address to the effective address(segment offset), which creates a reference to any byte location within the supported linear-addressspace. Linear addresses are often referred to as virtual addresses, and both terms are usedinterchangeably throughout this document.Linear Address = Segment Base Address + Effective AddressWhen the flat-memory model is used—as in 64-bit mode—a segment-base address is treated as 0.
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