Volume 2 System Programming (794096), страница 18
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3.13—July 2007AMD64 TechnologyThe simplest, most efficient method of memory management is the flat-memory model. In the flatmemory model, all segment base addresses have a value of 0 and the segment limits are fixed at 4Gbytes. The segmentation mechanism is still used each time a memory reference is made, but becausevirtual addresses are identical to effective addresses in this model, the segmentation mechanism iseffectively ignored. Translation of virtual (or effective) addresses to physical addresses takes placeusing the paging mechanism only.Because 64-bit mode disables segmentation, it uses a flat, paged-memory model for memorymanagement.
The 4 Gbyte segment limit is ignored in 64-bit mode. Figure 1-4 shows an example ofthis model.Virtual AddressSpaceEffective AddressPhysical AddressSpacePhysical AddressVirtual AddressPage Translation TablesPage FrameFlat SegmentPage Table Base AddressFigure 1-4.System-Programming Overview513-204.eps64-Bit Flat, Paged-Memory Model9AMD64 Technology24593—Rev. 3.13—July 20071.2.4 Real AddressingReal addressing is a legacy-mode form of address translation used in real mode. This simplified formof address translation is backward compatible with 8086-processor effective-to-physical addresstranslation.
In this mode, 16-bit effective addresses are mapped to 20-bit physical addresses, providinga 1-Mbyte physical-address space.Segment selectors are used in real-address translation, but not as an index into a descriptor table.Instead, the 16-bit segment-selector value is shifted left by 4 bits to form a 20-bit segment-baseaddress. The 16-bit effective address is added to this 20-bit segment base address to yield a 20-bitphysical address. If the sum of the segment base and effective address carries over into bit 20, that bitcan be optionally truncated to mimic the 20-bit address wrapping of the 8086 processor by using theA20M# input signal to mask the A20 address bit.Real-address translation supports a 1-Mbyte physical-address space using up to 64K segments alignedon 16-byte boundaries. Each segment is exactly 64K bytes long.
Figure 1-5 shows an example of realaddress translation.SelectorsCSDSES150FSEffective AddressGSSS190000019Effective Address0Selector0000+190Physical Address513-205.epsFigure 1-5.10Real-Address Memory ModelSystem-Programming Overview24593—Rev.
3.13—July 20071.3AMD64 TechnologyOperating ModesThe legacy x86 architecture provides four operating modes or environments that support varyingforms of memory management, virtual-memory and physical-memory sizes, and protection:••••Real Mode.Protected Mode.Virtual-8086 Mode.System Management Mode.The AMD64 architecture supports all these legacy modes, and it adds a new operating mode calledlong mode. Table 1-1 shows the differences between long mode and legacy mode. Software can movebetween all supported operating modes as shown in Figure 1-6 on page 12.
Each operating mode isdescribed in the following sections.Table 1-1. Operating ModesModeLongMode364-BitModeCompatibilityModeProtectedModeLegacyModeVirtual-8086ModeReal ModeSystemSoftwareRequiredApplicationRecompileRequiredyesNew64-bit OSLegacy32-bit OSLegacy16-bit OSnoDefaults1Address OperandSizeSize(bits)(bits)643232161632321616noRegisterExtensions2MaximumGPRWidth(bits)yes64no3232no161632Note:1. Defaults can be overridden in most modes using an instruction prefix or system control bit.2. Register extensions includes eight new GPRs and eight new XMM registers (also called SSE registers).3. Long mode supports only x86 protected mode.
It does not support x86 real mode or virtual-8086 mode.System-Programming Overview11AMD64 Technology24593—Rev. 3.13—July 2007Long ModeSMI#CS.L=164-bitModeCompatibilityModeCS.L=0RSMCS.L=0CR0.PG=0then EFER.LME=0EFER.LME=1, CR4.PAE=1then CR0.PG=1RSMRSMEFLAGS.VM=0ProtectedModeEFLAGS.VM=1SMI#SMI#SMI#ResetVirtual8086ModeRSMCR0.PE=1CR0.PE=0ResetResetSystemManagementModeRealModeResetSMI#RSM513-206.epsFigure 1-6. Operating Modes of the AMD64 Architecture1.3.1 Long ModeLong mode consists of two submodes: 64-bit mode and compatibility mode. 64-bit mode supportsseveral new features, including the ability to address 64-bit virtual-address space.
Compatibility modeprovides binary compatibility with existing 16-bit and 32-bit applications when running on 64-bitsystem software.Throughout this document, references to long mode refer collectively to both 64-bit mode andcompatibility mode. If a function is specific to either 64-bit mode or compatibility mode, then thosespecific names are used instead of the name long mode.Before enabling and activating long mode, system software must first enable protected mode. Theprocess of enabling and activating long mode is described in Chapter 14, “Processor Initialization and12System-Programming Overview24593—Rev. 3.13—July 2007AMD64 TechnologyLong Mode Activation.” Long mode features are described throughout this document, whereapplicable.1.3.2 64-Bit Mode64-bit mode, a submode of long mode, provides support for 64-bit system software and applications byadding the following new features:•••••64-bit virtual addresses (processor implementations can have fewer).Register extensions through a new instruction prefix (REX):- Adds eight GPRs (R8–R15).- Widens GPRs to 64 bits.- Adds eight 128-bit streaming SIMD extension (SSE) registers (XMM8–XMM15).64-bit instruction pointer (RIP).New RIP-relative data-addressing mode.Flat-segment address space with single code, data, and stack space.The mode is enabled by the system software on an individual code-segment basis.
Although codesegments are used to enable and disable 64-bit mode, the legacy segmentation mechanism is largelydisabled. Page translation is required for memory management purposes. Because 64-bit modesupports a 64-bit virtual-address space, it requires 64-bit system software and development tools.In 64-bit mode, the default address size is 64 bits, and the default operand size is 32 bits. The defaultscan be overridden on an instruction-by-instruction basis using instruction prefixes.
A new REX prefixis introduced for specifying a 64-bit operand size and the new registers.1.3.3 Compatibility ModeCompatibility mode, a submode of long mode, allows system software to implement binarycompatibility with existing 16-bit and 32-bit x86 applications. It allows these applications to run,without recompilation, under 64-bit system software in long mode, as shown in Table 1-1 on page 11.In compatibility mode, applications can only access the first 4 Gbytes of virtual-address space.Standard x86 instruction prefixes toggle between 16-bit and 32-bit address and operand sizes.Compatibility mode, like 64-bit mode, is enabled by system software on an individual code-segmentbasis. Unlike 64-bit mode, however, segmentation functions the same as in the legacy-x86architecture, using 16-bit or 32-bit protected-mode semantics.
From an application viewpoint,compatibility mode looks like a legacy protected-mode environment. From a system-softwareviewpoint, the long-mode mechanisms are used for address translation, interrupt and exceptionhandling, and system data-structures.System-Programming Overview13AMD64 Technology24593—Rev. 3.13—July 20071.3.4 Legacy ModesLegacy mode consists of three submodes: real mode, protected mode, and virtual-8086 mode.Protected mode can be either paged or unpaged. Legacy mode preserves binary compatibility not onlywith existing x86 16-bit and 32-bit applications but also with existing x86 16-bit and 32-bit systemsoftware.Real Mode.
In this mode, also called real-address mode, the processor supports a physical-memoryspace of 1 Mbyte and operand sizes of 16 bits (default) or 32 bits (with instruction prefixes). Interrupthandling and address generation are nearly identical to the 80286 processor's real mode.
Paging is notsupported. All software runs at privilege level 0.Real mode is entered after reset or processor power-up. The mode is not supported when the processoris operating in long mode because long mode requires that paged protected mode be enabled.Protected Mode. In this mode, the processor supports virtual-memory and physical-memory spacesof 4 Gbytes and operand sizes of 16 or 32 bits.
All segment translation, segment protection, andhardware multitasking functions are available. System software can use segmentation to relocateeffective addresses in virtual-address space. If paging is not enabled, virtual addresses are equal tophysical addresses. Paging can be optionally enabled to allow translation of virtual addresses tophysical addresses and to use the page-based memory-protection mechanisms.In protected mode, software runs at privilege levels 0, 1, 2, or 3.
Typically, application software runs atprivilege level 3, the system software runs at privilege levels 0 and 1, and privilege level 2 is availableto system software for other uses. The 16-bit version of this mode was first introduced in the 80286processor.Virtual-8086 Mode. Virtual-8086 mode allows system software to run 16-bit real-mode software on avirtualized-8086 processor. In this mode, software written for the 8086, 8088, 80186, or 80188processor can run as a privilege-level-3 task under protected mode.
The processor supports a virtualmemory space of 1 Mbytes and operand sizes of 16 bits (default) or 32 bits (with instruction prefixes),and it uses real-mode address translation.Virtual-8086 mode is enabled by setting the virtual-machine bit in the EFLAGS register(EFLAGS.VM). EFLAGS.VM can only be set or cleared when the EFLAGS register is loaded fromthe TSS as a result of a task switch, or by executing an IRET instruction from privileged software. ThePOPF instruction cannot be used to set or clear the EFLAGS.VM bit.Virtual-8086 mode is not supported when the processor is operating in long mode. When long mode isenabled, any attempt to enable virtual-8086 mode is silently ignored.14System-Programming Overview24593—Rev.
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