Volume 2 System Programming (794096), страница 17
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Inthis case, the linear address is identical to the effective address. In long mode, linear addresses must bein canonical address form, as described in “Canonical Address Form” on page 4.Physical Addresses. A physical address is a reference into the physical-address space, typicallymain memory. Physical addresses are translated from virtual addresses using page-translationmechanisms. See “Paging” on page 7 for information on how the paging mechanism is used forvirtual-address to physical-address translation. When the paging mechanism is not enabled, the virtual(linear) address is used as the physical address.1.1.2 Memory OrganizationThe AMD64 architecture organizes memory into virtual memory and physical memory.
Virtualmemory and physical-memory spaces can be (and usually are) different in size. Generally, the virtualaddress space is much larger than physical-address memory. System software relocates applicationsand data between physical memory and the system hard disk to make it appear that much morememory is available than really exists.
System software then uses the hardware memory-managementmechanisms to map the larger virtual-address space into the smaller physical-address space.Virtual Memory. Software uses virtual addresses to access locations within the virtual-memoryspace. System software is responsible for managing the relocation of applications and data in virtualmemory space using segment-memory management. System software is also responsible for mappingvirtual memory to physical memory through the use of page translation.
The AMD64 architecturesupports different virtual-memory sizes using the following address-translation modes:••Protected Mode—This mode supports 4 gigabytes of virtual-address space using 32-bit virtualaddresses.Long Mode—This mode supports 16 exabytes of virtual-address space using 64-bit virtualaddresses.System-Programming Overview3AMD64 Technology24593—Rev. 3.13—July 2007Physical Memory.
Physical addresses are used to directly access main memory. For a particularcomputer system, the size of the available physical-address space is equal to the amount of mainmemory installed in the system. The maximum amount of physical memory accessible depends on theprocessor implementation and on the address-translation mode. The AMD64 architecture supportsvarying physical-memory sizes using the following address-translation modes:•••Real-Address Mode—This mode, also called real mode, supports 1 megabyte of physical-addressspace using 20-bit physical addresses.
This address-translation mode is described in “RealAddressing” on page 10. Real mode is available only from legacy mode (see “Legacy Modes” onpage 14).Legacy Protected Mode—This mode supports several different address-space sizes, depending onthe translation mechanism used and whether extensions to those mechanisms are enabled.Legacy protected mode supports 4 gigabytes of physical-address space using 32-bit physicaladdresses. Both segment translation (see “Segmentation” on page 5) and page translation (see“Paging” on page 7) can be used to access the physical address space, when the processor isrunning in legacy protected mode.When the physical-address size extensions are enabled (see “Physical-Address Extensions (PAE)Bit” on page 119), the page-translation mechanism can be extended to support 52-bit physicaladdresses.
52-bit physical addresses allow up to 4 petabytes of physical-address space to besupported. (Currently, the AMD64 architecture supports 40-bit addresses in this mode, allowing upto 1 terabyte of physical-address space to be supported.Long Mode—This mode is unique to the AMD64 architecture. This mode supports up to 4petabytes of physical-address space using 52-bit physical addresses.
Long mode requires the use ofpage-translation and the physical-address size extensions (PAE).1.1.3 Canonical Address FormLong mode defines 64 bits of virtual-address space, but processor implementations can support less.Although some processor implementations do not use all 64 bits of the virtual address, they all checkbits 63 through the most-significant implemented bit to see if those bits are all zeros or all ones. Anaddress that complies with this property is in canonical address form. In most cases, a virtual-memoryreference that is not in canonical form causes a general-protection exception (#GP) to occur.
However,implied stack references where the stack address is not in canonical form causes a stack exception(#SS) to occur. Implied stack references include all push and pop instructions, and any instructionusing RSP or RBP as a base register.By checking canonical-address form, the AMD64 architecture prevents software from exploitingunused high bits of pointers for other purposes. Software complying with canonical-address form on aspecific processor implementation can run unchanged on long-mode implementations supportinglarger virtual-address spaces.4System-Programming Overview24593—Rev.
3.13—July 20071.2AMD64 TechnologyMemory ManagementMemory management consists of the methods by which addresses generated by software are translatedby segmentation and/or paging into addresses in physical memory. Memory management is not visibleto application software. It is handled by the system software and processor hardware.1.2.1 SegmentationSegmentation was originally created as a method by which system software could isolate softwareprocesses (tasks), and the data used by those processes, from one another in an effort to increase thereliability of systems running multiple processes simultaneously.The AMD64 architecture is designed to support all forms of legacy segmentation.
However, mostmodern system software does not use the segmentation features available in the legacy x86architecture. Instead, system software typically handles program and data isolation using page-levelprotection. For this reason, the AMD64 architecture dispenses with multiple segments in 64-bit modeand, instead, uses a flat-memory model. The elimination of segmentation allows new 64-bit systemsoftware to be coded more simply, and it supports more efficient management of multi-processing thanis possible in the legacy x86 architecture.Segmentation is, however, used in compatibility mode and legacy mode. Here, segmentation is a formof base memory-addressing that allows software and data to be relocated in virtual-address space off ofan arbitrary base address.
Software and data can be relocated in virtual-address space using one ormore variable-sized memory segments. The legacy x86 architecture provides several methods ofrestricting access to segments from other segments so that software and data can be protected frominterfering with each other.In compatibility and legacy modes, up to 16,383 unique segments can be defined. The base-addressvalue, segment size (called a limit), protection, and other attributes for each segment are contained in adata structure called a segment descriptor. Collections of segment descriptors are held in descriptortables. Specific segment descriptors are referenced or selected from the descriptor table using asegment selector register.
Six segment-selector registers are available, providing access to as many assix segments at a time.Figure 1-1 on page 6 shows an example of segmented memory. Segmentation is described inChapter 4, “Segmented Virtual Memory.”System-Programming Overview5AMD64 Technology24593—Rev. 3.13—July 2007Virtual AddressSpaceEffective AddressDescriptor TableVirtual AddressSelectorsCSLimitDSBaseESFSSegmentLimitGSBaseSSSegment513-201.epsFigure 1-1.Segmented-Memory ModelFlat Segmentation.
One special case of segmented memory is the flat-memory model. In the legacyflat-memory model, all segment-base addresses have a value of 0, and the segment limits are fixed at4 Gbytes. Segmentation cannot be disabled but use of the flat-memory model effectively disablessegment translation. The result is a virtual address that equals the effective address. Figure 1-2 onpage 7 shows an example of the flat-memory model.Software running in 64-bit mode automatically uses the flat-memory model. In 64-bit mode, thesegment base is treated as if it were 0, and the segment limit is ignored.
This allows an effectiveaddresses to access the full virtual-address space supported by the processor.6System-Programming Overview24593—Rev. 3.13—July 2007AMD64 TechnologyVirtual AddressSpaceEffective AddressVirtual AddressFlat Segment513-202.epsFigure 1-2. Flat Memory Model1.2.2 PagingPaging allows software and data to be relocated in physical-address space using fixed-size blockscalled physical pages. The legacy x86 architecture supports three different physical-page sizes of4 Kbytes, 2 Mbytes, and 4 Mbytes. As with segment translation, access to physical pages by lesserprivileged software can be restricted.Page translation uses a hierarchical data structure called a page-translation table to translate virtualpages into physical-pages.
The number of levels in the translation-table hierarchy can be as few as oneor as many as four, depending on the physical-page size and processor operating mode. Translationtables are aligned on 4-Kbyte boundaries. Physical pages must be aligned on 4-Kbyte, 2-Mbyte, or 4Mbyte boundaries, depending on the physical-page size.Each table in the translation hierarchy is indexed by a portion of the virtual-address bits. The entryreferenced by the table index contains a pointer to the base address of the next-lower-level table in thetranslation hierarchy.
In the case of the lowest-level table, its entry points to the physical-page baseaddress. The physical page is then indexed by the least-significant bits of the virtual address to yieldthe physical address.Figure 1-3 on page 8 shows an example of paged memory with three levels in the translation-tablehierarchy. Paging is described in Chapter 5, “Page Translation and Protection.”System-Programming Overview7AMD64 Technology24593—Rev. 3.13—July 2007Physical AddressSpaceVirtual AddressPhysical AddressTable 1Table 2Table 3Page Translation TablesPhysical PagePage Table Base Address513-203.epsFigure 1-3.Paged Memory ModelSoftware running in long mode is required to have page translation enabled.1.2.3 Mixing Segmentation and PagingMemory-management software can combine the use of segmented memory and paged memory.Because segmentation cannot be disabled, paged-memory management requires some minimuminitialization of the segmentation resources.
Paging can be completely disabled, so segmentedmemory management does not require initialization of the paging resources.Segments can range in size from a single byte to 4 Gbytes in length. It is therefore possible to mapmultiple segments to a single physical page and to map multiple physical pages to a single segment.Alignment between segment and physical-page boundaries is not required, but memory-managementsoftware is simplified when segment and physical-page boundaries are aligned.8System-Programming Overview24593—Rev.
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