Volume 2 System Programming (794096), страница 20
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Interrupts can be caused whensystem hardware signals an interrupt condition using one of the external-interrupt signals on theprocessor. Interrupts can also be caused by software that executes an interrupt instruction. Exceptionsoccur when the processor detects an abnormal condition as a result of executing an instruction. Theterm “interrupts” as used throughout this volume includes both interrupts and exceptions when thedistinction is unnecessary.System software not only sets up the interrupt handlers, but it must also create and initialize the datastructures the processor uses to execute an interrupt handler when an interrupt occurs.
The datastructures include the code-segment descriptors for the interrupt-handler software and any datasegment descriptors for data and stack accesses. Interrupt-gate descriptors must also be supplied.Interrupt gates point to interrupt-handler code-segment descriptors, and the entry point in an interrupthandler. Interrupt gates are stored in the interrupt-descriptor table. The code-segment and datasegment descriptors are stored in the global-descriptor table and, optionally, the local-descriptor table.When an interrupt occurs, the processor uses the interrupt vector to find the appropriate interrupt gatein the interrupt-descriptor table. The gate points to the interrupt-handler code segment and entry point,and the processor transfers control to that location.
Before invoking the interrupt handler, the processorsaves information required to return to the interrupted program. For details on how the processortransfers control to interrupt handlers, see “Legacy Protected-Mode Interrupt Control Transfers” onpage 229, and “Long-Mode Interrupt Control Transfers” on page 239.System-Programming Overview19AMD64 Technology24593—Rev. 3.13—July 2007Table 1-2 shows the supported interrupts and exceptions, ordered by their vector number. Refer to“Vectors” on page 206 for a complete description of each interrupt, and a description of the interruptmechanism.Table 1-2.Interrupts and ExceptionsVector0Integer Divide-by-Zero Exception1Debug Exception2Non-Maskable-Interrupt3Breakpoint Exception (INT 3)4Overflow Exception (INTO instruction)5Bound-Range Exception (BOUND instruction)6Invalid-Opcode Exception7Device-Not-Available Exception8Double-Fault Exception9Coprocessor-Segment-Overrun Exception (reserved inAMD64)10Invalid-TSS Exception11Segment-Not-Present Exception12Stack Exception13General-Protection Exception14Page-Fault Exception15(Reserved)16x87 Floating-Point Exception17Alignment-Check Exception18Machine-Check Exception19SIMD Floating-Point Exception0-255Any1.7DescriptionInterrupt InstructionsHardware Maskable InterruptsAdditional System-Programming Facilities1.7.1 Hardware MultitaskingA task is any program that the processor can execute, suspend, and later resume executing at the pointof suspension.
During the time a task is suspended, other tasks are allowed to execute. Each task has itsown execution space, consisting of a code segment, data segments, and a stack segment for eachprivilege level. Tasks can also have their own virtual-memory environment managed by the pagetranslation mechanism. The state information defining this execution space is stored in the task-statesegment (TSS) maintained for each task.20System-Programming Overview24593—Rev. 3.13—July 2007AMD64 TechnologySupport for hardware multitasking is provided by implementations of the AMD64 architecture whensoftware is running in legacy mode.
Hardware multitasking provides automated mechanisms forswitching tasks, saving the execution state of the suspended task, and restoring the execution state ofthe resumed task. When hardware multitasking is used to switch tasks, the processor takes thefollowing actions:••••The processor automatically suspends execution of the task, allowing any executing instructions tocomplete and save their results.The execution state of a task is saved in the task TSS.The execution state of a new task is loaded into the processor from its TSS.The processor begins executing the new task at the location specified in the new task TSS.Use of hardware-multitasking features is optional in legacy mode. Generally, modern operatingsystems do not use the hardware-multitasking features, and instead perform task management entirelyin software.
Long mode does not support hardware multitasking at all.Whether hardware multitasking is used or not, system software must create and initialize at least onetask-state segment data-structure. This requirement holds for both long-mode and legacy-modesoftware. The single task-state segment holds critical pieces of the task execution environment and isreferenced during certain control transfers.Detailed information on hardware multitasking is available in Chapter 12, “Task Management,” alongwith a full description of the requirements that must be met in initializing a task-state segment whenhardware multitasking is not used.1.7.2 Machine CheckImplementations of the AMD64 architecture support the machine-check exception.
This exception isuseful in system applications with stringent requirements for reliability, availability, and serviceability.The exception allows specialized system-software utilities to report hardware errors that are generallysevere and non-recoverable. Providing the capability to report such errors can allow complex systemproblems to be pinpointed rapidly.The machine-check exception is described in Chapter 9, “Machine Check Mechanism.” Much of theerror-reporting capabilities is implementation dependent.
For more information, developers ofmachine-check error-reporting software should also refer to the BIOS writer’s guide for a specificimplementation.1.7.3 Software DebuggingA software-debugging mechanism is provided in hardware to help software developers quickly isolateprogramming errors. This capability can be used to debug system software and application softwarealike. Only privileged software can access the debugging facilities. Generally, software-debug supportis provided by a privileged application program rather than by the operating system itself.The facilities supported by the AMD64 architecture allow debugging software to perform thefollowing:System-Programming Overview21AMD64 Technology••••••••24593—Rev.
3.13—July 2007Set breakpoints on specific instructions within a program.Set breakpoints on an instruction-address match.Set breakpoints on a data-address match.Set breakpoints on specific I/O-port addresses.Set breakpoints to occur on task switches when hardware multitasking is used.Single step an application instruction-by-instruction.Single step only branches and interrupts.Record a history of branches and interrupts taken by a program.The debugging facilities are fully described in “Software-Debug Resources” on page 325. Someprocessors provide additional, implementation-specific debug support.
For more information, refer tothe BIOS writer’s guide for the specific implementation.1.7.4 Performance MonitoringFor many software developers, the ability to identify and eliminate performance bottlenecks from aprogram is nearly as important as quickly isolating programming errors. Implementations of theAMD64 architecture provide hardware performance-monitoring resources that can be used by specialsoftware applications to identify such bottlenecks. Non-privileged software can access theperformance monitoring facilities, but only if privileged software grants that access.The performance-monitoring facilities allow the counting of events, or the duration of events.Performance-analysis software can use the data to calculate the frequency of certain events, or the timespent performing specific activities.
That information can be used to suggest areas for improvementand the types of optimizations that are helpful.The performance-monitoring facilities are fully described in “Performance Optimization” onpage 339. The specific events that can be monitored are generally implementation specific. For moreinformation, refer to the BIOS writer’s guide for the specific implementation.22System-Programming Overview24593—Rev.
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