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Incorporated numerous factualcorrections and updates.February 20053.10Corrected Table 8-6, “General-Protection Exception Conditions”‚ onpage 217. Added SSE3 information. Clarified and corrected information onthe CPUID instruction and feature identification. Added information on theRDTSCP instruction. Clarified information about MTRRs and PATs inmultiprocessing systems.September20033.09Corrected numerous minor typographical errors.April 20033.08Clarified terms in section on FXSAVE/FXSTOR. Corrected several minorerrors of omission. Documentation of CR0.NW bit has been corrected.Several register diagrams and figure labels have been corrected.Description of shared cache lines has been clarified in 7.3, ”MemoryCoherency and Protocol” on page 165.September20023.07Made numerous small grammatical changes and factual clarifications.Added Revision History.Revision HistoryxxvAMD64 Technologyxxvi24593—Rev.
3.13—July 2007Revision History24593—Rev. 3.13—July 2007AMD64 TechnologyPrefaceAbout This BookThis book is part of a multivolume work entitled the AMD64 Architecture Programmer’s Manual. Thistable lists each volume and its order number.TitleOrder No.Volume 1: Application Programming24592Volume 2: System Programming24593Volume 3: General-Purpose and System Instructions24594Volume 4: 128-Bit Media Instructions26568Volume 5: 64-Bit Media and x87 Floating-Point Instructions26569AudienceThis volume (Volume 2) is intended for programmers writing operating systems, loaders, linkers,device drivers, or system utilities. It assumes an understanding of AMD64 architecture applicationlevel programming as described in Volume 1.This volume describes the AMD64 architecture’s resources and functions that are managed by systemsoftware, including operating-mode control, memory management, interrupts and exceptions, task andstate-change management, system-management mode (including power management), multiprocessor support, debugging, and processor initialization.Application-programming topics are described in Volume 1.
Details about each instruction aredescribed in volumes 3, 4, and 5.Contact InformationTo submit questions or comments concerning this document, contact our technical documentation staffat AMD64.Feedback@amd.com.OrganizationThis volume begins with an overview of system programming and differences between the x86 andAMD64 architectures. This is followed by chapters that describe the following details of systemprogramming:PrefacexxviiAMD64 Technology24593—Rev.
3.13—July 2007••System Resources—The system registers and processor ID (CPUID) functions.Segmented Virtual Memory—The segmented-memory models supported by the architecture andtheir associated data structures and protection checks.•Page Translation and Protection—The page-translation functions supported by the architectureand their associated data structures and protection checks.System-Management Instructions—The instructions used to manage system functions.Memory System—The memory-system hierarchy and its resources and protocols, includingmemory-characterization, caching, and buffering functions.Exceptions and Interrupts—Details about the types and causes of exceptions and interrupts, andthe methods of transferring control during these events.Machine-Check Mechanism—The resources and functions that support detection and handling ofmachine-check errors.System-Management Mode—The resources and functions that support system-management mode(SMM), including power-management functions.128-Bit, 64-Bit, and x87 Programming—The resources and functions that support use (byapplication software) and state-saving (by the operation system) of the 128-bit media, 64-bitmedia, and x87 floating-point instructions.Multiple-Processor Management—The features of the instruction set and the system resources andfunctions that support multiprocessing environments.Debug and Performance Resources—The system resources and functions that support softwaredebugging and performance monitoring.Legacy Task Management—Support for the legacy hardware multitasking functions, includingregister resources and data structures.Processor Initialization and Long-Mode Activation—The methods by which system softwareinitializes and changes operating modes.Mixing Code Across Operating Modes—Things to remember when running programs in differentoperating modes.Secure Virtual Machine—The system resources that support virtualization development anddeployment.••••••••••••There are appendices describing details of model-specific registers (MSRs) and machine-checkimplementations.
Definitions assumed throughout this volume are listed below. The index at the end ofthis volume cross-references topics within the volume. For other topics relating to the AMD64architecture, see the tables of contents and indexes of the other volumes.xxviiiPreface24593—Rev. 3.13—July 2007AMD64 TechnologyDefinitionsSome of the following definitions assume a knowledge of the legacy x86 architecture. See “RelatedDocuments” on page xxxix for descriptions of the legacy x86 architecture.Terms and Notation1011bA binary value—in this example, a 4-bit value.F0EAhA hexadecimal value—in this example a 2-byte value.[1,2)A range that includes the left-most value (in this case, 1) but excludes the right-most value (in thiscase, 2).7–4A bit range, from bit 7 to 4, inclusive.
The high-order bit is shown first.128-bit media instructionsInstructions that use the 128-bit XMM registers. These are a combination of the SSE and SSE2instruction sets.64-bit media instructionsInstructions that use the 64-bit MMX registers. These are primarily a combination of MMX and3DNow!™ instruction sets, with some additional instructions from the SSE and SSE2 instructionsets.16-bit modeLegacy mode or compatibility mode in which a 16-bit address size is active. See legacy mode andcompatibility mode.32-bit modeLegacy mode or compatibility mode in which a 32-bit address size is active.
See legacy mode andcompatibility mode.64-bit modeA submode of long mode. In 64-bit mode, the default address size is 64 bits and new features, suchas register extensions, are supported for system and application software.#GP(0)Notation indicating a general-protection exception (#GP) with error code of 0.PrefacexxixAMD64 Technology24593—Rev. 3.13—July 2007absoluteSaid of a displacement that references the base of a code segment rather than an instruction pointer.Contrast with relative.ASIDAddress space identifier.biased exponentThe sum of a floating-point value’s exponent and a constant bias for a particular floating-point datatype. The bias makes the range of the biased exponent always positive, which allows reciprocationwithout overflow.byteEight bits.clearTo write a bit value of 0.
Compare set.compatibility modeA submode of long mode. In compatibility mode, the default address size is 32 bits, and legacy 16bit and 32-bit applications run without modification.commitTo irreversibly write, in program order, an instruction’s result to software-visible storage, such as aregister (including flags), the data cache, an internal write buffer, or memory.CPLCurrent privilege level.CR0–CR4A register range, from register CR0 through CR4, inclusive, with the low-order register first.CR0.PE = 1Notation indicating that the PE bit of the CR0 register has a value of 1.directReferencing a memory location whose address is included in the instruction’s syntax as animmediate operand.
The address may be an absolute or relative address. Compare indirect.dirty dataData held in the processor’s caches or internal buffers that is more recent than the copy held inmain memory.displacementA signed value that is added to the base of a segment (absolute addressing) or an instruction pointer(relative addressing). Same as offset.xxxPreface24593—Rev. 3.13—July 2007AMD64 TechnologydoublewordTwo words, or four bytes, or 32 bits.double quadwordEight words, or 16 bytes, or 128 bits. Also called octword.DS:rSIThe contents of a memory location whose segment address is in the DS register and whose offsetrelative to that segment is in the rSI register.EFER.LME = 0Notation indicating that the LME bit of the EFER register has a value of 0.effective address sizeThe address size for the current instruction after accounting for the default address size and anyaddress-size override prefix.effective operand sizeThe operand size for the current instruction after accounting for the default operand size and anyoperand-size override prefix.elementSee vector.exceptionAn abnormal condition that occurs as the result of executing an instruction.
The processor’sresponse to an exception depends on the type of the exception. For all exceptions except 128-bitmedia SIMD floating-point exceptions and x87 floating-point exceptions, control is transferred tothe handler (or service routine) for that exception, as defined by the exception’s vector. Forfloating-point exceptions defined by the IEEE 754 standard, there are both masked and unmaskedresponses.
When unmasked, the exception handler is called, and when masked, a default responseis provided instead of calling the handler.FF /0Notation indicating that FF is the first byte of an opcode, and a subopcode in the ModR/M byte hasa value of 0.flushAn often ambiguous term meaning (1) writeback, if modified, and invalidate, as in “flush the cacheline,” or (2) invalidate, as in “flush the pipeline,” or (3) change a value, as in “flush to zero.”GDTGlobal descriptor table.PrefacexxxiAMD64 Technology24593—Rev.
3.13—July 2007GIFGlobal interrupt flag.IDTInterrupt descriptor table.IGNIgnore. Field is ignored.indirectReferencing a memory location whose address is in a register or other memory location. Theaddress may be an absolute or relative address. Compare direct.IRBThe virtual-8086 mode interrupt-redirection bitmap.ISTThe long-mode interrupt-stack table.IVTThe real-address mode interrupt-vector table.LDTLocal descriptor table.legacy x86The legacy x86 architecture. See “Related Documents” on page xxxix for descriptions of thelegacy x86 architecture.legacy modeAn operating mode of the AMD64 architecture in which existing 16-bit and 32-bit applications andoperating systems run without modification.
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