Volume 2 System Programming (794096), страница 26
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Bit 29. Ignored. This bit can be set to 1 or cleared to 0, but its value isignored. The NW bit exists only for legacy purposes.Cache Disable (CD) Bit. Bit 30. When CD is cleared to 0, the internal caches are enabled. When CDis set to 1, no new data or instructions are brought into the internal caches. However, the processor stillaccesses the internal caches when CD=1 under the following situations:••Reads that hit in an internal cache cause the data to be read from the internal cache that reported thehit.Writes that hit in an internal cache cause the cache line that reported the hit to be written back tomemory and invalidated in the cache.Cache misses do not affect the internal caches when CD=1.
Software can prevent cache access bywriting back and invalidating the caches before setting CD to 1 (this avoids caching the instructionsthat set CD to 1).Setting CD to 1 also causes the processor to ignore the page-level cache-control bits (PWT and PCD)when paging is enabled. These bits are located in the page-translation tables and CR3 register. See“Page-Level Writethrough (PWT) Bit” on page 137 and “Page-Level Cache Disable (PCD) Bit” onpage 137 for information on page-level cache control.See “Memory Caches” on page 174 for information on the internal caches.Paging Enable (PG) Bit. Bit 31. Software enables page translation by setting PG to 1, and disablespage translation by clearing PG to 0.
Page translation cannot be enabled unless the processor is inprotected mode (CR0.PE=1). If software attempts to set PG to 1 when PE is cleared to 0, the processorcauses a general-protection exception (#GP).See “Page Translation Overview” on page 115 for information on the page-translation mechanism.Reserved Bits. Bits 28–19, 17, 15–6, and 63–32.
When writing the CR0 register, software should setthe values of reserved bits to the values found during the previous CR0 read. No attempt should bemade to change reserved bits, and software should never rely on the values of reserved bits. In longmode, bits 63–32 are reserved and must be written with zero, otherwise a #GP occurs.3.1.2 CR2 and CR3 RegistersThe CR2 (page-fault linear address) register, shown in Figure 3-2 on page 46 and Figure 3-3 onpage 46, and the CR3 (page-translation-table base address) register, shown in Figure 3-4 andFigure 3-5 on page 46, and Figure 3-6 on page 46, are used only by the page-translation mechanism.System Resources45AMD64 Technology24593—Rev. 3.13—July 2007310Page-Fault Virtual AddressFigure 3-2.
Control Register 2 (CR2)—Legacy-Mode6332Page-Fault Virtual Address310Page-Fault Virtual AddressFigure 3-3.Control Register 2 (CR2)—Long ModeSee “CR2 Register” on page 218 for a description of the CR2 register.The CR3 register is used to point to the base address of the highest-level page-translation table.3112 11Page-Directory-Table Base Address5Reserved4 3 20P PC W ReservedD TFigure 3-4.
Control Register 3 (CR3)—Legacy-Mode Non-PAE Paging315Page-Directory-Pointer-Table Base AddressFigure 3-5.Control Register 3 (CR3)—Legacy-Mode PAE Paging6352 51Reserved, MBZ32Page-Map Level-4 Table Base Address(This is an architectural limit. A given implementation may support fewer bits.)3112 11Page-Map Level-4 Table Base AddressFigure 3-6.464 3 20P PC W ReservedD T5Reserved4 3 20P PC W ReservedD TControl Register 3 (CR3)—Long ModeSystem Resources24593—Rev. 3.13—July 2007AMD64 TechnologyThe legacy CR3 register is described in “CR3 Register” on page 120, and the long-mode CR3 registeris described in “CR3” on page 128.3.1.3 CR4 RegisterThe CR4 register is shown in Figure 3-7 on page 47. In legacy mode, the CR4 register is identical tothe low 32 bits of the register shown in Figure 3-7 on page 47 (CR4 bits 31–0).
The features controlledby the bits in the CR4 register are model-specific extensions. Except for the performance-counterextensions (PCE) feature, software can use the CPUID instruction to verify that each feature issupported before using that feature.6332Reserved, MBZ31Reserved, MBZBits63–11109876543210MnemonicReservedOSXMMEXCPTOSFXSRPCEPGEMCEPAEPSEDETSDPVIVME11 109OOSFSXSRXDescriptionReserved, Must be ZeroOperating System Unmasked Exception SupportOperating System FXSAVE/FXRSTOR SupportPerformance-Monitoring Counter EnablePage-Global EnableMachine Check EnablePhysical-Address ExtensionPage Size ExtensionsDebugging ExtensionsTime Stamp DisableProtected-Mode Virtual InterruptsVirtual-8086 Mode ExtensionsFigure 3-7.8 7 6 5P P M PC G C AE E E E4 3 2 1 0PT P VDSS V MEED I ER/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WControl Register 4 (CR4)The function of the CR4 control bits are (all bits are read/write):Virtual-8086 Mode Extensions (VME) Bit.
Bit 0. Setting VME to 1 enables hardware-supportedperformance enhancements for software running in virtual-8086 mode. Clearing VME to 0 disablesthis support. The enhancements enabled when VME=1 include:•Virtualized, maskable, external-interrupt control and notification using the VIF and VIP bits in therFLAGS register. Virtualizing affects the operation of several instructions that manipulate therFLAGS.IF bit.System Resources47AMD64 Technology•24593—Rev.
3.13—July 2007Selective intercept of software interrupts (INTn instructions) using the interrupt-redirection bitmapin the TSS.Protected-Mode Virtual Interrupts (PVI) Bit. Bit 1. Setting PVI to 1 enables support for protected-mode virtual interrupts. Clearing PVI to 0 disables this support. When PVI=1, hardware support of twobits in the rFLAGS register, VIF and VIP, is enabled.Only the STI and CLI instructions are affected by enabling PVI. Unlike the case when CR0.VME=1,the interrupt-redirection bitmap in the TSS cannot be used for selective INTn interception.PVI enhancements are also supported in long mode. See “Virtual Interrupts” on page 245 for moreinformation on using PVI.Time-Stamp Disable (TSD) Bit.
Bit 2. The TSD bit allows software to control the privilege level atwhich the time-stamp counter can be read. When TSD is cleared to 0, software running at any privilegelevel can read the time-stamp counter using the RDTSC or RDTSCP instructions. When TSD is set to1, only software running at privilege-level 0 can execute the RDTSC or RDTSCP instructions.Debugging Extensions (DE) Bit. Bit 3. Setting the DE bit to 1 enables the I/O breakpoint capabilityand enforces treatment of the DR4 and DR5 registers as reserved.
Software that accesses DR4 or DR5when DE=1 causes a invalid opcode exception (#UD).When the DE bit is cleared to 0, I/O breakpoint capabilities are disabled. Software references to theDR4 and DR5 registers are aliased to the DR6 and DR7 registers, respectively.Page-Size Extensions (PSE) Bit. Bit 4. Setting PSE to 1 enables the use of 4-Mbyte physical pages.With PSE=1, the physical-page size is selected between 4 Kbytes and 4 Mbytes using the pagedirectory entry page-size field (PS). Clearing PSE to 0 disables the use of 4-Mbyte physical pages andrestricts all physical pages to 4 Kbytes.The PSE bit has no effect when physical-address extensions are enabled (CR4.PAE=1).
Because longmode requires CR4.PAE=1, the PSE bit is ignored when the processor is running in long mode.See “4-Mbyte Page Translation” on page 123 for more information on 4-Mbyte page translation.Physical-Address Extension (PAE) Bit. Bit 5. Setting PAE to 1 enables the use of physical-addressextensions and 2-Mbyte physical pages. Clearing PAE to 0 disables these features.With PAE=1, the page-translation data structures are expanded from 32 bits to 64 bits, allowing thetranslation of up to 52-bit physical addresses. Also, the physical-page size is selectable between4 Kbytes and 2 Mbytes using the page-directory-entry page-size field (PS). Long mode requires PAEto be enabled in order to use the 64-bit page-translation data structures to translate 64-bit virtualaddresses to 52-bit physical addresses.See “PAE Paging” on page 124 for more information on physical-address extensions.48System Resources24593—Rev.
3.13—July 2007AMD64 TechnologyMachine-Check Enable (MCE) Bit. Bit 6. Setting MCE to 1 enables the machine-check exceptionmechanism. Clearing this bit to 0 disables the mechanism. When enabled, a machine-check exception(#MC) occurs when an uncorrectable machine-check error is encountered.Regardless of whether machine-check exceptions are enabled, the processor records enabled-errorswhen they occur. Error-reporting is performed by the machine-check error-reporting register banks.Each bank includes a control register for enabling error reporting and a status register for capturingerrors. Correctable machine-check errors are also reported, but they do not cause a machine-checkexception.See Chapter 9, “Machine Check Mechanism,” for a description of the machine-check mechanism, theregisters used, and the types of errors captured by the mechanism.Page-Global Enable (PGE) Bit.
Bit 7. When page translation is enabled, system-softwareperformance can often be improved by making some page translations global to all tasks andprocedures. Setting PGE to 1 enables the global-page mechanism. Clearing this bit to 0 disables themechanism.When PGE is enabled, system software can set the global-page (G) bit in the lowest level of the pagetranslation hierarchy to 1, indicating that the page translation is global. Page translations marked asglobal are not invalidated in the TLB when the page-translation-table base address (CR3) is updated.When the G bit is cleared, the page translation is not global.
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