Volume 2 System Programming (794096), страница 27
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All supported physical-page sizes alsosupport the global-page mechanism. See “Global Pages” on page 140 for information on using theglobal-page mechanism.Performance-Monitoring Counter Enable (PCE) Bit. Bit 8. Setting PCE to 1 allows softwarerunning at any privilege level to use the RDPMC instruction. Software uses the RDPMC instruction toread the four performance-monitoring MSRs, PerfCTR[3:0]. Clearing PCE to 0 allows only the mostprivileged software (CPL=0) to use the RDPMC instruction.FXSAVE/FXRSTOR Support (OSFXSR) Bit.
Bit 9. System software must set the OSFXSR bit to 1to enable use of the 128-bit media instructions. When this bit is set to 1, it also indicates that systemsoftware uses the FXSAVE and FXRSTOR instructions to save and restore the processor state for thex87, 64-bit media, and 128-bit media instructions.Clearing the OSFXSR bit to 0 indicates that 128-bit media instructions cannot be used. Attempts to usethose instructions while this bit is clear result in an invalid-opcode exception (#UD).
Software cancontinue to use the FXSAVE/FXRSTOR instructions for saving and restoring the processor state forthe x87 and 64-bit media instructions.Unmasked Exception Support (OSXMMEXCPT) Bit. Bit 10. System software must set theOSXMMEXCPT bit to 1 when it supports the SIMD floating-point exception (#XF) for handling ofunmasked 128-bit media floating-point errors.
Clearing the OSXMMEXCPT bit to 0 indicates the#XF handler is not supported. When OSXMMEXCPT=0, unmasked 128-bit media floating-pointexceptions cause an invalid-opcode exception (#UD). See “SIMD Floating-Point Exception Causes”in Volume 1 for more information on 128-bit media unmasked floating-point exceptions.System Resources49AMD64 Technology24593—Rev. 3.13—July 20073.1.4 CR1 and CR5–CR7 RegistersControl registers CR1, CR5–CR7, and CR9–CR15 are reserved.
Attempts by software to use theseregisters result in an undefined-opcode exception (#UD).3.1.5 64-Bit-Mode Extended Control RegistersIn 64-bit mode, additional encodings for control registers are available. The REX.R bit, in a REXprefix, is used to modify the ModRM reg field when that field encodes a control register, as shown in“REX Prefixes” in Volume 3. These additional encodings enable the processor to address CR8–CR15.One additional control register, CR8, is defined in 64-bit mode for all hardware implementations, asdescribed in “CR8 (Task Priority Register, TPR),” below.
Access to the CR9–CR15 registers isimplementation-dependent. Any attempt to access an unimplemented register results in an invalidopcode exception (#UD).3.1.6 CR8 (Task Priority Register, TPR)The AMD64 architecture introduces a new control register, CR8, defined as the task priority register(TPR). The register is accessible in 64-bit mode using the REX prefix. See “External InterruptPriorities” on page 226 for a description of the TPR and how system software can use the TPR forcontrolling external interrupts.3.1.7 RFLAGS RegisterThe RFLAGS register contains two different types of information:••Control bits provide system-software controls and directional information for string operations.Some of these bits can have privilege-level restrictions.Status bits provide information resulting from logical and arithmetic operations.
These are writtenby the processor and can be read by software running at any privilege level.Figure 3-8 on page 51 shows the format of the RFLAGS register. The legacy EFLAGS register isidentical to the low 32 bits of the register shown in Figure 3-8 (RFLAGS bits 31–0). The term rFLAGSis used to refer to the 16-bit, 32-bit, or 64-bit flags register, depending on context.50System Resources24593—Rev. 3.13—July 2007AMD64 Technology6332Reserved, RAZ31Reserved, RAZBits63–22212019181716151413-1211109876543210MnemonicReservedIDVIPVIFACVMRFReservedNTIOPLOFDFIFTFSFZFReservedAFReservedPFReservedCF22 21 20VIIDP19 18 17 16 15 14 13 12 11 10 9VA V RNO D II0IOPLC M FTF F FFDescriptionReserved, Read as ZeroID FlagVirtual Interrupt PendingVirtual Interrupt FlagAlignment CheckVirtual-8086 ModeResume FlagReserved, Read as ZeroNested TaskI/O Privilege LevelOverflow FlagDirection FlagInterrupt FlagTrap FlagSign FlagZero FlagReserved, Read as ZeroAuxiliary FlagReserved, Read as ZeroParity FlagReserved, Read as OneCarry FlagFigure 3-8.876543210TFSFZF0AF0PF1CFR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WRFLAGS RegisterThe functions of the RFLAGS control and status bits used by application software are described in“Flags Register” in Volume 1.
The functions of RFLAGS system bits are (unless otherwise noted, allbits are read/write):Trap Flag (TF) Bit. Bit 8. Software sets the TF bit to 1 to enable single-step mode during softwaredebug. Clearing this bit to 0 disables single-step mode.When single-step mode is enabled, a debug exception (#DB) occurs after each instruction completesexecution. Single stepping begins with the instruction following the instruction that sets TF. Singlestepping is disabled (TF=0) when the #DB exception occurs or when any exception or interrupt occurs.System Resources51AMD64 Technology24593—Rev. 3.13—July 2007See “Single Stepping” on page 337 for information on using the single-step mode during debugging.Interrupt Flag (IF) Bit.
Bit 9. Software sets the IF bit to 1 to enable maskable interrupts. Clearing thisbit to 0 causes the processor to ignore maskable interrupts. The state of the IF bit does not affect theresponse of a processor to non-maskable interrupts, software-interrupt instructions, or exceptions.The ability to modify the IF bit depends on several factors:••••The current privilege-level (CPL)The I/O privilege level (RFLAGS.IOPL)Whether or not virtual-8086 mode extensions are enabled (CR4.VME=1)Whether or not protected-mode virtual interrupts are enabled (CR4.PVI=1)See “Masking External Interrupts” on page 205 for information on interrupt masking. See “Accessingthe RFLAGs Register” on page 152 for information on the specific instructions used to modify the IFbit.I/O Privilege Level Field (IOPL) Field. Bits 13–12.
The IOPL field specifies the privilege levelrequired to execute I/O address-space instructions (i.e., instructions that address the I/O space ratherthan memory-mapped I/O, such as IN, OUT, INS, OUTS, etc.). For software to execute theseinstructions, the current privilege-level (CPL) must be equal to or higher than (lower numerical valuethan) the privilege specified by IOPL (CPL <= IOPL). If the CPL is lower than (higher numerical valuethan) that specified by the IOPL (CPL > IOPL), the processor causes a general-protection exception(#GP) when software attempts to execute an I/O instruction. See “Protected-Mode I/O” in Volume 1for information on how IOPL controls access to address-space I/O.Virtual-8086 mode uses IOPL to control virtual interrupts and the IF bit when virtual-8086 modeextensions are enabled (CR4.VME=1).
The protected-mode virtual-interrupt mechanism (PVI) alsouses IOPL to control virtual interrupts and the IF bit when PVI is enabled (CR4.PVI=1). See “VirtualInterrupts” on page 245 for information on how IOPL is used by the virtual interrupt mechanism.Nested Task (NT) Bit. Bit 14, IRET reads the NT bit to determine whether the current task is nestedwithin another task. When NT is set to 1, the current task is nested within another task. When NT iscleared to 0, the current task is at the top level (not nested).The processor sets the NT bit during a task switch resulting from a CALL, interrupt, or exceptionthrough a task gate. When an IRET is executed from legacy mode while the NT bit is set, a task switchoccurs. See “Task Switches Using Task Gates” on page 321 for information on switching tasks usingtask gates, and “Nesting Tasks” on page 323 for information on task nesting.Resume Flag (RF) Bit.
Bit 16. The RF bit allows an instruction to be restarted following aninstruction breakpoint resulting in a debug exception (#DB). This bit prevents multiple debugexceptions from occurring on the same instruction.52System Resources24593—Rev. 3.13—July 2007AMD64 TechnologyThe processor clears the RF bit after every instruction is successfully executed, except when theinstruction is:••An IRET that sets the RF bit.JMP, CALL, or INTn through a task gate.In both of the above cases, RF is not cleared to 0 until the next instruction successfully executes.When an exception occurs (or when a string instruction is interrupted), the processor normally setsRF=1 in the rFLAGS image saved on the interrupt stack. However, when a #DB exception occurs as aresult of an instruction breakpoint, the processor clears the RF bit to 0 in the interrupt-stack rFLAGSimage.For instruction restart to work properly following an instruction breakpoint, the #DB exceptionhandler must set RF to 1 in the interrupt-stack rFLAGS image.
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