Volume 2B Instruction Set Reference N-Z (794102), страница 73
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2B0110 0111INSTRUCTION FORMATS AND ENCODINGSTable B-15. General Purpose Instruction Formats and Encodingsfor 64-Bit Mode (Contd.)Instruction and FormatEncodingLOCK1111 0000operand size0110 0110CS segment override0010 1110DS segment override0011 1110ES segment override0010 0110FS segment override0110 0100GS segment override0110 0101SS segment override0011 0110B.3PENTIUM® PROCESSOR FAMILY INSTRUCTIONFORMATS AND ENCODINGSThe following table shows formats and encodings introduced by the Pentiumprocessor family.Table B-16. Pentium Processor Family Instruction Formats and Encodings,Non-64-Bit ModesInstruction and FormatEncodingCMPXCHG8B – Compare and Exchange 8 BytesEDX:EAX with memory640000 1111 : 1100 0111 : mod 001 r/mTable B-17. Pentium Processor Family Instruction Formats and Encodings, 64-BitModeInstruction and FormatEncodingCMPXCHG8B/CMPXCHG16B – Compare andExchange BytesEDX:EAX with memory640000 1111 : 1100 0111 : mod 001 r/mRDX:RAX with memory1280100 10XB 0000 1111 : 1100 0111 : mod001 r/mVol.
2B B-53INSTRUCTION FORMATS AND ENCODINGSB.464-BIT MODE INSTRUCTION ENCODINGS FOR SIMDINSTRUCTION EXTENSIONSNon-64-bit mode instruction encodings for MMX Technology, SSE, SSE2, and SSE3are covered by applying these rules to Table B-19 through Table B-30. Table B-32lists special encodings (instructions that do not follow the rules below).1. The REX instruction has no effect:••••On immediatesIf both operands are MMX registersOn MMX registers and XMM registersIf an MMX register is encoded in the reg field of the ModR/M byte2.
If a memory operand is encoded in the r/m field of the ModR/M byte, REX.X andREX.B may be used for encoding the memory operand.3. If a general-purpose register is encoded in the r/m field of the ModR/M byte,REX.B may be used for register encoding and REX.W may be used to encode the64-bit operand size.4. If an XMM register operand is encoded in the reg field of the ModR/M byte, REX.Rmay be used for register encoding. If an XMM register operand is encoded in ther/m field of the ModR/M byte, REX.B may be used for register encoding.B.5MMX INSTRUCTION FORMATS AND ENCODINGSMMX instructions, except the EMMS instruction, use a format similar to the 2-byteIntel Architecture integer format.
Details of subfield encodings within these formatsare presented below.B.5.1Granularity Field (gg)The granularity field (gg) indicates the size of the packed operands that the instruction is operating on. When this field is used, it is located in bits 1 and 0 of the secondopcode byte. Table B-18 shows the encoding of the gg field.Table B-18. Encoding of Granularity of Data Field (gg)gg00B-54 Vol. 2BGranularity of DataPacked Bytes01Packed Words10Packed Doublewords11QuadwordINSTRUCTION FORMATS AND ENCODINGSB.5.2MMX Technology and General-Purpose Register Fields(mmxreg and reg)When MMX technology registers (mmxreg) are used as operands, they are encodedin the ModR/M byte in the reg field (bits 5, 4, and 3) and/or the R/M field (bits 2, 1,and 0).If an MMX instruction operates on a general-purpose register (reg), the register isencoded in the R/M field of the ModR/M byte.B.5.3MMX Instruction Formats and Encodings TableTable B-19 shows the formats and encodings of the integer instructions.Table B-19.
MMX Instruction Formats and EncodingsInstruction and FormatEMMS – Empty MMX technology stateEncoding0000 1111:01110111MOVD – Move doublewordreg to mmreg0000 1111:0110 1110: 11 mmxreg regreg from mmxreg0000 1111:0111 1110: 11 mmxreg regmem to mmxreg0000 1111:0110 1110: mod mmxreg r/mmem from mmxreg0000 1111:0111 1110: mod mmxreg r/mMOVQ – Move quadwordmmxreg2 to mmxreg10000 1111:0110 1111: 11 mmxreg1 mmxreg2mmxreg2 from mmxreg10000 1111:0111 1111: 11 mmxreg1 mmxreg2mem to mmxreg0000 1111:0110 1111: mod mmxreg r/mmem from mmxreg0000 1111:0111 1111: mod mmxreg r/mPACKSSDW1– Pack dword to word data(signed with saturation)mmxreg2 to mmxreg10000 1111:0110 1011: 11 mmxreg1 mmxreg2memory to mmxreg0000 1111:0110 1011: mod mmxreg r/mPACKSSWB1– Pack word to byte data(signed with saturation)mmxreg2 to mmxreg10000 1111:0110 0011: 11 mmxreg1 mmxreg2memory to mmxreg0000 1111:0110 0011: mod mmxreg r/mPACKUSWB1– Pack word to byte data(unsigned with saturation)mmxreg2 to mmxreg10000 1111:0110 0111: 11 mmxreg1 mmxreg2Vol.
2B B-55INSTRUCTION FORMATS AND ENCODINGSTable B-19. MMX Instruction Formats and Encodings (Contd.)Instruction and Formatmemory to mmxregEncoding0000 1111:0110 0111: mod mmxreg r/mPADD – Add with wrap-aroundmmxreg2 to mmxreg10000 1111: 1111 11gg: 11 mmxreg1 mmxreg2memory to mmxreg0000 1111: 1111 11gg: mod mmxreg r/mPADDS – Add signed with saturationmmxreg2 to mmxreg10000 1111: 1110 11gg: 11 mmxreg1 mmxreg2memory to mmxreg0000 1111: 1110 11gg: mod mmxreg r/mPADDUS – Add unsigned with saturationmmxreg2 to mmxreg10000 1111: 1101 11gg: 11 mmxreg1 mmxreg2memory to mmxreg0000 1111: 1101 11gg: mod mmxreg r/mPAND – Bitwise Andmmxreg2 to mmxreg10000 1111:1101 1011: 11 mmxreg1 mmxreg2memory to mmxreg0000 1111:1101 1011: mod mmxreg r/mPANDN – Bitwise AndNotmmxreg2 to mmxreg10000 1111:1101 1111: 11 mmxreg1 mmxreg2memory to mmxreg0000 1111:1101 1111: mod mmxreg r/mPCMPEQ – Packed compare for equalitymmxreg1 with mmxreg20000 1111:0111 01gg: 11 mmxreg1 mmxreg2mmxreg with memory0000 1111:0111 01gg: mod mmxreg r/mPCMPGT – Packed compare greater(signed)mmxreg1 with mmxreg20000 1111:0110 01gg: 11 mmxreg1 mmxreg2mmxreg with memory0000 1111:0110 01gg: mod mmxreg r/mPMADDWD – Packed multiply addmmxreg2 to mmxreg10000 1111:1111 0101: 11 mmxreg1 mmxreg2memory to mmxreg0000 1111:1111 0101: mod mmxreg r/mPMULHUW – Packed multiplication, storehigh word (unsigned)mmxreg2 to mmxreg10000 1111: 1110 0100: 11 mmxreg1 mmxreg2memory to mmxreg0000 1111: 1110 0100: mod mmxreg r/mB-56 Vol.
2BINSTRUCTION FORMATS AND ENCODINGSTable B-19. MMX Instruction Formats and Encodings (Contd.)Instruction and FormatEncodingPMULHW – Packed multiplication, storehigh wordmmxreg2 to mmxreg10000 1111:1110 0101: 11 mmxreg1 mmxreg2memory to mmxreg0000 1111:1110 0101: mod mmxreg r/mPMULLW – Packed multiplication, store lowwordmmxreg2 to mmxreg10000 1111:1101 0101: 11 mmxreg1 mmxreg2memory to mmxreg0000 1111:1101 0101: mod mmxreg r/mPOR – Bitwise Ormmxreg2 to mmxreg10000 1111:1110 1011: 11 mmxreg1 mmxreg2memory to mmxreg0000 1111:1110 1011: mod mmxreg r/mPSLL2– Packed shift left logicalmmxreg1 by mmxreg20000 1111:1111 00gg: 11 mmxreg1 mmxreg2mmxreg by memory0000 1111:1111 00gg: mod mmxreg r/mmmxreg by immediate0000 1111:0111 00gg: 11 110 mmxreg: imm8dataPSRA2 – Packed shift right arithmeticmmxreg1 by mmxreg20000 1111:1110 00gg: 11 mmxreg1 mmxreg2mmxreg by memory0000 1111:1110 00gg: mod mmxreg r/mmmxreg by immediate0000 1111:0111 00gg: 11 100 mmxreg: imm8dataPSRL2 – Packed shift right logicalmmxreg1 by mmxreg20000 1111:1101 00gg: 11 mmxreg1 mmxreg2mmxreg by memory0000 1111:1101 00gg: mod mmxreg r/mmmxreg by immediate0000 1111:0111 00gg: 11 010 mmxreg: imm8dataPSUB – Subtract with wrap-aroundmmxreg2 from mmxreg10000 1111:1111 10gg: 11 mmxreg1 mmxreg2memory from mmxreg0000 1111:1111 10gg: mod mmxreg r/mPSUBS – Subtract signed with saturationmmxreg2 from mmxreg10000 1111:1110 10gg: 11 mmxreg1 mmxreg2memory from mmxreg0000 1111:1110 10gg: mod mmxreg r/mVol.
2B B-57INSTRUCTION FORMATS AND ENCODINGSTable B-19. MMX Instruction Formats and Encodings (Contd.)Instruction and FormatEncodingPSUBUS – Subtract unsigned withsaturationmmxreg2 from mmxreg10000 1111:1101 10gg: 11 mmxreg1 mmxreg2memory from mmxreg0000 1111:1101 10gg: mod mmxreg r/mPUNPCKH – Unpack high data to next largertypemmxreg2 to mmxreg10000 1111:0110 10gg: 11 mmxreg1 mmxreg2memory to mmxreg0000 1111:0110 10gg: mod mmxreg r/mPUNPCKL – Unpack low data to next largertypemmxreg2 to mmxreg10000 1111:0110 00gg: 11 mmxreg1 mmxreg2memory to mmxreg0000 1111:0110 00gg: mod mmxreg r/mPXOR – Bitwise Xormmxreg2 to mmxreg10000 1111:1110 1111: 11 mmxreg1 mmxreg2memory to mmxreg0000 1111:1110 1111: mod mmxreg r/mNOTES:1. The pack instructions perform saturation from signed packed data of one type to signed orunsigned data of the next smaller type.2.
The format of the shift instructions has one additional format to support shifting by immediateshift-counts. The shift operations are not supported equally for all data types.B.6P6 FAMILY INSTRUCTION FORMATS ANDENCODINGSTable B-20 shows the formats and encodings for several instructions that were introduced into the IA-32 architecture in the P6 family processors.Table B-20. Formats and Encodings of P6 Family InstructionsInstruction and FormatEncodingCMOVcc – Conditional Moveregister2 to register10000 1111: 0100 tttn : 11 reg1 reg2memory to register0000 1111 : 0100 tttn : mod reg r/mB-58 Vol. 2BINSTRUCTION FORMATS AND ENCODINGSTable B-20. Formats and Encodings of P6 Family Instructions (Contd.)Instruction and FormatEncodingFCMOVcc – Conditional Move on EFLAGRegister Condition Codesmove if below (B)11011 010 : 11 000 ST(i)move if equal (E)11011 010 : 11 001 ST(i)move if below or equal (BE)11011 010 : 11 010 ST(i)move if unordered (U)11011 010 : 11 011 ST(i)move if not below (NB)11011 011 : 11 000 ST(i)move if not equal (NE)11011 011 : 11 001 ST(i)move if not below or equal (NBE)11011 011 : 11 010 ST(i)move if not unordered (NU)11011 011 : 11 011 ST(i)FCOMI – Compare Real and Set EFLAGS11011 011 : 11 110 ST(i)FXRSTOR – Restore x87 FPU, MMX, SSE,and SSE2 State10000 1111:1010 1110: modA 001 r/mFXSAVE – Save x87 FPU, MMX, SSE, andSSE2 State10000 1111:1010 1110: modA 000 r/mSYSENTER – Fast System Call0000 1111:0011 0100SYSEXIT – Fast Return from Fast SystemCall0000 1111:0011 0101NOTES:1.
For FXSAVE and FXRSTOR, “mod = 11” is reserved.B.7SSE INSTRUCTION FORMATS AND ENCODINGSThe SSE instructions use the ModR/M format and are preceded by the 0FH prefixbyte. In general, operations are not duplicated to provide two directions (that is,separate load and store variants).The following three tables (Tables B-21, B-22, and B-23) show the formats andencodings for the SSE SIMD floating-point, SIMD integer, and cacheability andmemory ordering instructions, respectively. Some SSE instructions require a mandatory prefix (66H, F2H, F3H) as part of the two-byte opcode. Mandatory prefixes areincluded in the tables.Vol. 2B B-59INSTRUCTION FORMATS AND ENCODINGSTable B-21. Formats and Encodings of SSE Floating-Point InstructionsInstruction and FormatEncodingADDPS—Add Packed Single-PrecisionFloating-Point Valuesxmmreg to xmmreg0000 1111:0101 1000:11 xmmreg1 xmmreg2mem to xmmreg0000 1111:0101 1000: mod xmmreg r/mADDSS—Add Scalar Single-PrecisionFloating-Point Valuesxmmreg to xmmreg1111 0011:0000 1111:01011000:11 xmmreg1xmmreg2mem to xmmreg1111 0011:0000 1111:01011000: mod xmmreg r/mANDNPS—Bitwise Logical AND NOT ofPacked Single-Precision Floating-PointValuesxmmreg to xmmreg0000 1111:0101 0101:11 xmmreg1 xmmreg2mem to xmmreg0000 1111:0101 0101: mod xmmreg r/mANDPS—Bitwise Logical AND of PackedSingle-Precision Floating-Point Valuesxmmreg to xmmreg0000 1111:0101 0100:11 xmmreg1 xmmreg2mem to xmmreg0000 1111:0101 0100: mod xmmreg r/mCMPPS—Compare Packed SinglePrecision Floating-Point Valuesxmmreg to xmmreg, imm80000 1111:1100 0010:11 xmmreg1 xmmreg2:imm8mem to xmmreg, imm80000 1111:1100 0010: mod xmmreg r/m: imm8CMPSS—Compare Scalar SinglePrecision Floating-Point Valuesxmmreg to xmmreg, imm81111 0011:0000 1111:1100 0010:11 xmmreg1xmmreg2: imm8mem to xmmreg, imm81111 0011:0000 1111:1100 0010: mod xmmregr/m: imm8COMISS—Compare Scalar OrderedSingle-Precision Floating-Point Valuesand Set EFLAGSxmmreg to xmmreg0000 1111:0010 1111:11 xmmreg1 xmmreg2mem to xmmreg0000 1111:0010 1111: mod xmmreg r/mB-60 Vol.
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