Volume 2B Instruction Set Reference N-Z (794102), страница 69
Текст из файла (страница 69)
The multi-byte NOP instruction does not alter the content of the register and will not issue amemoryoperation.Vol. 2B B-23INSTRUCTION FORMATS AND ENCODINGSB.2.1General Purpose Instruction Formats and Encodings for64-Bit ModeTable B-15 shows machine instruction formats and encodings for general purposeinstructions in 64-bit mode.Table B-14. Special SymbolsSymbolApplicationSIf the value of REX.W. is 1, it overrides the presence of 66H.wThe value of bit W.
in REX is has no effect.Table B-15. General Purpose Instruction Formats and Encodingsfor 64-Bit ModeInstruction and FormatEncodingADC – ADD with Carryregister1 to register20100 0R0B : 0001 000w : 11 reg1 reg2qwordregister1 to qwordregister20100 1R0B : 0001 0001 : 11 qwordreg1qwordreg2register2 to register10100 0R0B : 0001 001w : 11 reg1 reg2qwordregister1 to qwordregister20100 1R0B : 0001 0011 : 11 qwordreg1qwordreg2memory to register0100 0RXB : 0001 001w : mod reg r/mmemory to qwordregister0100 1RXB : 0001 0011 : mod qwordreg r/mregister to memory0100 0RXB : 0001 000w : mod reg r/mqwordregister to memory0100 1RXB : 0001 0001 : mod qwordreg r/mimmediate to register0100 000B : 1000 00sw : 11 010 reg :immediateimmediate to qwordregister0100 100B : 1000 0001 : 11 010 qwordreg :imm32immediate to qwordregister0100 1R0B : 1000 0011 : 11 010 qwordreg :imm8immediate to AL, AX, or EAX0001 010w : immediate dataimmediate to RAX0100 1000 : 0000 0101 : imm32immediate to memory0100 00XB : 1000 00sw : mod 010 r/m :immediateimmediate32 to memory640100 10XB : 1000 0001 : mod 010 r/m :imm32B-24 Vol.
2BINSTRUCTION FORMATS AND ENCODINGSTable B-15. General Purpose Instruction Formats and Encodingsfor 64-Bit Mode (Contd.)Instruction and Formatimmediate8 to memory64Encoding0100 10XB : 1000 0031 : mod 010 r/m : imm8ADD – Addregister1 to register20100 0R0B : 0000 000w : 11 reg1 reg2qwordregister1 to qwordregister20100 1R0B 0000 0000 : 11 qwordreg1qwordreg2register2 to register10100 0R0B : 0000 001w : 11 reg1 reg2qwordregister1 to qwordregister20100 1R0B 0000 0010 : 11 qwordreg1qwordreg2memory to register0100 0RXB : 0000 001w : mod reg r/mmemory64 to qwordregister0100 1RXB : 0000 0000 : mod qwordreg r/mregister to memory0100 0RXB : 0000 000w : mod reg r/mqwordregister to memory640100 1RXB : 0000 0011 : mod qwordreg r/mimmediate to register0100 0000B : 1000 00sw : 11 000 reg :immediate dataimmediate32 to qwordregister0100 100B : 1000 0001 : 11 010 qwordreg :immimmediate to AL, AX, or EAX0000 010w : immediate8immediate to RAX0100 1000 : 0000 0101 : imm32immediate to memory0100 00XB : 1000 00sw : mod 000 r/m :immediateimmediate32 to memory640100 10XB : 1000 0001 : mod 010 r/m :imm32immediate8 to memory640100 10XB : 1000 0011 : mod 010 r/m : imm8AND – Logical ANDregister1 to register20100 0R0B 0010 000w : 11 reg1 reg2qwordregister1 to qwordregister20100 1R0B 0010 0001 : 11 qwordreg1qwordreg2register2 to register10100 0R0B 0010 001w : 11 reg1 reg2register1 to register20100 1R0B 0010 0011 : 11 qwordreg1qwordreg2memory to register0100 0RXB 0010 001w : mod reg r/mmemory64 to qwordregister0100 1RXB : 0010 0011 : mod qwordreg r/mVol.
2B B-25INSTRUCTION FORMATS AND ENCODINGSTable B-15. General Purpose Instruction Formats and Encodingsfor 64-Bit Mode (Contd.)Instruction and FormatEncodingregister to memory0100 0RXB : 0010 000w : mod reg r/mqwordregister to memory640100 1RXB : 0010 0001 : mod qwordreg r/mimmediate to register0100 000B : 1000 00sw : 11 100 reg :immediateimmediate32 to qwordregister0100 100B 1000 0001 : 11 100 qwordreg :imm32immediate to AL, AX, or EAX0010 010w : immediateimmediate32 to RAX0100 1000 0010 1001 : imm32immediate to memory0100 00XB : 1000 00sw : mod 100 r/m :immediateimmediate32 to memory640100 10XB : 1000 0001 : mod 100 r/m :immediate32immediate8 to memory640100 10XB : 1000 0011 : mod 100 r/m :imm8BSF – Bit Scan Forwardregister1, register20100 0R0B 0000 1111 : 1011 1100 : 11 reg1reg2qwordregister1, qwordregister20100 1R0B 0000 1111 : 1011 1100 : 11qwordreg1 qwordreg2memory, register0100 0RXB 0000 1111 : 1011 1100 : mod regr/mmemory64, qwordregister0100 1RXB 0000 1111 : 1011 1100 : modqwordreg r/mBSR – Bit Scan Reverseregister1, register20100 0R0B 0000 1111 : 1011 1101 : 11 reg1reg2qwordregister1, qwordregister20100 1R0B 0000 1111 : 1011 1101 : 11qwordreg1 qwordreg2memory, register0100 0RXB 0000 1111 : 1011 1101 : mod regr/mmemory64, qwordregister0100 1RXB 0000 1111 : 1011 1101 : modqwordreg r/mBSWAP – Byte SwapB-26 Vol.
2B0000 1111 : 1100 1 regINSTRUCTION FORMATS AND ENCODINGSTable B-15. General Purpose Instruction Formats and Encodingsfor 64-Bit Mode (Contd.)Instruction and FormatBSWAP – Byte SwapEncoding0100 100B 0000 1111 : 1100 1 qwordregBT – Bit Testregister, immediate0100 000B 0000 1111 : 1011 1010 : 11 100reg: imm8qwordregister, immediate80100 100B 1111 : 1011 1010 : 11 100qwordreg: imm8 datamemory, immediate0100 00XB 0000 1111 : 1011 1010 : mod100 r/m : imm8memory64, immediate80100 10XB 0000 1111 : 1011 1010 : mod100 r/m : imm8 dataregister1, register20100 0R0B 0000 1111 : 1010 0011 : 11 reg2reg1qwordregister1, qwordregister20100 1R0B 0000 1111 : 1010 0011 : 11qwordreg2 qwordreg1memory, reg0100 0RXB 0000 1111 : 1010 0011 : mod regr/mmemory, qwordreg0100 1RXB 0000 1111 : 1010 0011 : modqwordreg r/mBTC – Bit Test and Complementregister, immediate0100 000B 0000 1111 : 1011 1010 : 11 111reg: imm8qwordregister, immediate80100 100B 0000 1111 : 1011 1010 : 11 111qwordreg: imm8memory, immediate0100 00XB 0000 1111 : 1011 1010 : mod111 r/m : imm8memory64, immediate80100 10XB 0000 1111 : 1011 1010 : mod111 r/m : imm8register1, register20100 0R0B 0000 1111 : 1011 1011 : 11 reg2reg1qwordregister1, qwordregister20100 1R0B 0000 1111 : 1011 1011 : 11qwordreg2 qwordreg1memory, register0100 0RXB 0000 1111 : 1011 1011 : mod regr/mVol.
2B B-27INSTRUCTION FORMATS AND ENCODINGSTable B-15. General Purpose Instruction Formats and Encodingsfor 64-Bit Mode (Contd.)Instruction and Formatmemory, qwordregEncoding0100 1RXB 0000 1111 : 1011 1011 : modqwordreg r/mBTR – Bit Test and Resetregister, immediate0100 000B 0000 1111 : 1011 1010 : 11 110reg: imm8qwordregister, immediate80100 100B 0000 1111 : 1011 1010 : 11 110qwordreg: imm8memory, immediate0100 00XB 0000 1111 : 1011 1010 : mod110 r/m : imm8memory64, immediate80100 10XB 0000 1111 : 1011 1010 : mod110 r/m : imm8register1, register20100 0R0B 0000 1111 : 1011 0011 : 11 reg2reg1qwordregister1, qwordregister20100 1R0B 0000 1111 : 1011 0011 : 11qwordreg2 qwordreg1memory, register0100 0RXB 0000 1111 : 1011 0011 : mod regr/mmemory64, qwordreg0100 1RXB 0000 1111 : 1011 0011 : modqwordreg r/mBTS – Bit Test and Setregister, immediate0100 000B 0000 1111 : 1011 1010 : 11 101reg: imm8qwordregister, immediate80100 100B 0000 1111 : 1011 1010 : 11 101qwordreg: imm8memory, immediate0100 00XB 0000 1111 : 1011 1010 : mod101 r/m : imm8memory64, immediate80100 10XB 0000 1111 : 1011 1010 : mod101 r/m : imm8register1, register20100 0R0B 0000 1111 : 1010 1011 : 11 reg2reg1qwordregister1, qwordregister20100 1R0B 0000 1111 : 1010 1011 : 11qwordreg2 qwordreg1B-28 Vol.
2BINSTRUCTION FORMATS AND ENCODINGSTable B-15. General Purpose Instruction Formats and Encodingsfor 64-Bit Mode (Contd.)Instruction and FormatEncodingmemory, register0100 0RXB 0000 1111 : 1010 1011 : mod regr/mmemory64, qwordreg0100 1RXB 0000 1111 : 1010 1011 : modqwordreg r/mCALL – Call Procedure (in same segment)direct1110 1000 : displacement32register indirect0100 WR00w 1111 1111 : 11 010 regmemory indirect0100 W0XBw 1111 1111 : mod 010 r/mCALL – Call Procedure (in other segment)indirect1111 1111 : mod 011 r/mindirect0100 10XB 0100 1000 1111 1111 : mod 011r/mCBW – Convert Byte to Word1001 1000CDQ – Convert Doubleword to Qword+1001 1001CDQE – RAX, Sign-Extend of EAX0100 1000 1001 1001CLC – Clear Carry Flag1111 1000CLD – Clear Direction Flag1111 1100CLI – Clear Interrupt Flag1111 1010CLTS – Clear Task-Switched Flag in CR00000 1111 : 0000 0110CMC – Complement Carry Flag1111 0101CMP – Compare Two Operandsregister1 with register20100 0R0B 0011 100w : 11 reg1 reg2qwordregister1 with qwordregister20100 1R0B 0011 1001 : 11 qwordreg1qwordreg2register2 with register10100 0R0B 0011 101w : 11 reg1 reg2qwordregister2 with qwordregister10100 1R0B 0011 101w : 11 qwordreg1qwordreg2memory with register0100 0RXB 0011 100w : mod reg r/mmemory64 with qwordregister0100 1RXB 0011 1001 : mod qwordreg r/mregister with memory0100 0RXB 0011 101w : mod reg r/mqwordregister with memory640100 1RXB 0011 101w1 : mod qwordreg r/mVol.
2B B-29INSTRUCTION FORMATS AND ENCODINGSTable B-15. General Purpose Instruction Formats and Encodingsfor 64-Bit Mode (Contd.)Instruction and FormatEncodingimmediate with register0100 000B 1000 00sw : 11 111 reg : immimmediate32 with qwordregister0100 100B 1000 0001 : 11 111 qwordreg :imm64immediate with AL, AX, or EAX0011 110w : immimmediate32 with RAX0100 1000 0011 1101 : imm32immediate with memory0100 00XB 1000 00sw : mod 111 r/m : immimmediate32 with memory640100 1RXB 1000 0001 : mod 111 r/m : imm64immediate8 with memory640100 1RXB 1000 0011 : mod 111 r/m : imm8CMPS/CMPSB/CMPSW/CMPSD/CMPSQ –Compare String Operandscompare string operands [ X at DS:(E)SI with Yat ES:(E)DI ]1010 011wqword at address RSI with qword at addressRDI0100 1000 1010 0111CMPXCHG – Compare and Exchangeregister1, register20000 1111 : 1011 000w : 11 reg2 reg1byteregister1, byteregister20100 000B 0000 1111 : 1011 0000 : 11bytereg2 reg1qwordregister1, qwordregister20100 100B 0000 1111 : 1011 0001 : 11qwordreg2 reg1memory, register0000 1111 : 1011 000w : mod reg r/mmemory8, byteregister0100 00XB 0000 1111 : 1011 0000 : modbytereg r/mmemory64, qwordregister0100 10XB 0000 1111 : 1011 0001 : modqwordreg r/mCPUID – CPU Identification0000 1111 : 1010 0010CQO – Sign-Extend RAX0100 1000 1001 1001CWD – Convert Word to Doubleword1001 1001CWDE – Convert Word to Doubleword1001 1000DEC – Decrement by 1register0100 000B 1111 111w : 11 001 regqwordregister0100 100B 1111 1111 : 11 001 qwordregB-30 Vol.
2BINSTRUCTION FORMATS AND ENCODINGSTable B-15. General Purpose Instruction Formats and Encodingsfor 64-Bit Mode (Contd.)Instruction and FormatEncodingmemory0100 00XB 1111 111w : mod 001 r/mmemory640100 10XB 1111 1111 : mod 001 r/mDIV – Unsigned DivideAL, AX, or EAX by register0100 000B 1111 011w : 11 110 regDivide RDX:RAX by qwordregister0100 100B 1111 0111 : 11 110 qwordregAL, AX, or EAX by memory0100 00XB 1111 011w : mod 110 r/mDivide RDX:RAX by memory640100 10XB 1111 0111 : mod 110 r/mENTER – Make Stack Frame for High LevelProcedure1100 1000 : 16-bit displacement : 8-bit level(L)HLT – Halt1111 0100IDIV – Signed DivideAL, AX, or EAX by register0100 000B 1111 011w : 11 111 regRDX:RAX by qwordregister0100 100B 1111 0111 : 11 111 qwordregAL, AX, or EAX by memory0100 00XB 1111 011w : mod 111 r/mRDX:RAX by memory640100 10XB 1111 0111 : mod 111 r/mIMUL – Signed MultiplyAL, AX, or EAX with register0100 000B 1111 011w : 11 101 regRDX:RAX <- RAX with qwordregister0100 100B 1111 0111 : 11 101 qwordregAL, AX, or EAX with memory0100 00XB 1111 011w : mod 101 r/mRDX:RAX <- RAX with memory640100 10XB 1111 0111 : mod 101 r/mregister1 with register20000 1111 : 1010 1111 : 11 : reg1 reg2qwordregister1 <- qwordregister1 withqwordregister20100 1R0B 0000 1111 : 1010 1111 : 11 :qwordreg1 qwordreg2register with memory0100 0RXB 0000 1111 : 1010 1111 : mod regr/mqwordregister <- qwordregisterwithmemory640100 1RXB 0000 1111 : 1010 1111 : modqwordreg r/mregister1 with immediate to register20100 0R0B 0110 10s1 : 11 reg1 reg2 : immqwordregister1 <- qwordregister2 with signextended immediate80100 1R0B 0110 1011 : 11 qwordreg1qwordreg2 : imm8qwordregister1 <- qwordregister2 withimmediate320100 1R0B 0110 1001 : 11 qwordreg1qwordreg2 : imm32Vol.
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