Volume 2B Instruction Set Reference N-Z (794102), страница 70
Текст из файла (страница 70)
2B B-31INSTRUCTION FORMATS AND ENCODINGSTable B-15. General Purpose Instruction Formats and Encodingsfor 64-Bit Mode (Contd.)Instruction and FormatEncodingmemory with immediate to register0100 0RXB 0110 10s1 : mod reg r/m : immqwordregister <- memory64 with signextended immediate80100 1RXB 0110 1011 : mod qwordreg r/m :imm8qwordregister <- memory64 withimmediate320100 1RXB 0110 1001 : mod qwordreg r/m :imm32IN – Input From Portfixed port1110 010w : port numbervariable port1110 110wINC – Increment by 1reg0100 000B 1111 111w : 11 000 regqwordreg0100 100B 1111 1111 : 11 000 qwordregmemory0100 00XB 1111 111w : mod 000 r/mmemory640100 10XB 1111 1111 : mod 000 r/mINS – Input from DX Port0110 110wINT n – Interrupt Type n1100 1101 : typeINT – Single-Step Interrupt 31100 1100INTO – Interrupt 4 on Overflow1100 1110INVD – Invalidate Cache0000 1111 : 0000 1000INVLPG – Invalidate TLB Entry0000 1111 : 0000 0001 : mod 111 r/mIRETO – Interrupt Return1100 1111Jcc – Jump if Condition is Met8-bit displacement0111 tttn : 8-bit displacementdisplacements (excluding 16-bit relativeoffsets)0000 1111 : 1000 tttn : displacement32JCXZ/JECXZ – Jump on CX/ECX ZeroAddress-size prefix differentiates JCXZ andJECXZ1110 0011 : 8-bit displacementJMP – Unconditional Jump (to same segment)short1110 1011 : 8-bit displacementdirect1110 1001 : displacement32register indirect0100 W00Bw : 1111 1111 : 11 100 regB-32 Vol.
2BINSTRUCTION FORMATS AND ENCODINGSTable B-15. General Purpose Instruction Formats and Encodingsfor 64-Bit Mode (Contd.)Instruction and Formatmemory indirectEncodingw0100 W0XB : 1111 1111 : mod 100 r/mJMP – Unconditional Jump (to other segment)indirect intersegment0100 00XB : 1111 1111 : mod 101 r/m64-bit indirect intersegment0100 10XB : 1111 1111 : mod 101 r/mLAR – Load Access Rights Bytefrom register0100 0R0B : 0000 1111 : 0000 0010 : 11reg1 reg2from dwordregister to qwordregister, maskedby 00FxFF00H0100 WR0B : 0000 1111 : 0000 0010 : 11qwordreg1 dwordreg2from memory0100 0RXB : 0000 1111 : 0000 0010 : modreg r/mfrom memory32 to qwordregister, masked by00FxFF00H0100 WRXB 0000 1111 : 0000 0010 : modr/mLEA – Load Effective Addressin wordregister/dwordregister0100 0RXB : 1000 1101 : modA reg r/min qwordregister0100 1RXB : 1000 1101 : modA qwordreg r/mLEAVE – High Level Procedure Exit1100 1001LFS – Load Pointer to FSFS:r16/r32 with far pointer from memory0100 0RXB : 0000 1111 : 1011 0100 : modAreg r/mFS:r64 with far pointer from memory0100 1RXB : 0000 1111 : 1011 0100 : modAqwordreg r/mLGDT – Load Global Descriptor Table Register0100 10XB : 0000 1111 : 0000 0001 : modA010 r/mLGS – Load Pointer to GSGS:r16/r32 with far pointer from memory0100 0RXB : 0000 1111 : 1011 0101 : modAreg r/mGS:r64 with far pointer from memory0100 1RXB : 0000 1111 : 1011 0101 : modAqwordreg r/mLIDT – Load Interrupt Descriptor TableRegister0100 10XB : 0000 1111 : 0000 0001 : modA011 r/mLLDT – Load Local Descriptor Table RegisterVol.
2B B-33INSTRUCTION FORMATS AND ENCODINGSTable B-15. General Purpose Instruction Formats and Encodingsfor 64-Bit Mode (Contd.)Instruction and FormatEncodingLDTR from register0100 000B : 0000 1111 : 0000 0000 : 11 010regLDTR from memory0100 00XB :0000 1111 : 0000 0000 : mod010 r/mLMSW – Load Machine Status Wordfrom register0100 000B : 0000 1111 : 0000 0001 : 11 110regfrom memory0100 00XB :0000 1111 : 0000 0001 : mod110 r/mLOCK – Assert LOCK# Signal Prefix1111 0000LODS/LODSB/LODSW/LODSD/LODSQ – LoadString Operandat DS:(E)SI to AL/EAX/EAXat (R)SI to RAX1010 110w0100 1000 1010 1101LOOP – Loop Countif count != 0, 8-bit displacement1110 0010if count !=0, RIP + 8-bit displacement signextended to 64-bits0100 1000 1110 0010LOOPE – Loop Count while Zero/Equalif count != 0 & ZF =1, 8-bit displacement1110 0001if count !=0 & ZF = 1, RIP + 8-bit displacementsign-extended to 64-bits0100 1000 1110 0001LOOPNE/LOOPNZ – Loop Count while notZero/Equalif count != 0 & ZF = 0, 8-bit displacement1110 0000if count !=0 & ZF = 0, RIP + 8-bit displacementsign-extended to 64-bits0100 1000 1110 0000LSL – Load Segment Limitfrom registerfrom qwordregisterfrom memory16B-34 Vol.
2B0000 1111 : 0000 0011 : 11 reg1 reg20100 1R00 0000 1111 : 0000 0011 : 11qwordreg1 reg20000 1111 : 0000 0011 : mod reg r/mINSTRUCTION FORMATS AND ENCODINGSTable B-15. General Purpose Instruction Formats and Encodingsfor 64-Bit Mode (Contd.)Instruction and Formatfrom memory64Encoding0100 1RXB 0000 1111 : 0000 0011 : modqwordreg r/mLSS – Load Pointer to SSSS:r16/r32 with far pointer from memory0100 0RXB : 0000 1111 : 1011 0010 : modAreg r/mSS:r64 with far pointer from memory0100 1WXB : 0000 1111 : 1011 0010 : modAqwordreg r/mLTR – Load Task Registerfrom register0100 0R00 : 0000 1111 : 0000 0000 : 11 011regfrom memory0100 00XB : 0000 1111 : 0000 0000 : mod011 r/mMOV – Move Dataregister1 to register20100 0R0B : 1000 100w : 11 reg1 reg2qwordregister1 to qwordregister20100 1R0B 1000 1001 : 11 qwordeg1qwordreg2register2 to register10100 0R0B : 1000 101w : 11 reg1 reg2qwordregister2 to qwordregister10100 1R0B 1000 1011 : 11 qwordreg1qwordreg2memory to reg0100 0RXB : 1000 101w : mod reg r/mmemory64 to qwordregister0100 1RXB 1000 1011 : mod qwordreg r/mreg to memory0100 0RXB : 1000 100w : mod reg r/mqwordregister to memory640100 1RXB 1000 1001 : mod qwordreg r/mimmediate to register0100 000B : 1100 011w : 11 000 reg : immimmediate32 to qwordregister (zero extend)0100 100B 1100 0111 : 11 000 qwordreg :imm32immediate to register (alternate encoding)0100 000B : 1011 w reg : immimmediate64 to qwordregister (alternateencoding)0100 100B 1011 1000 reg : imm64immediate to memory0100 00XB : 1100 011w : mod 000 r/m : immimmediate32 to memory64 (zero extend)0100 10XB 1100 0111 : mod 000 r/m : imm32memory to AL, AX, or EAX0100 0000 : 1010 000w : displacementmemory64 to RAX0100 1000 1010 0001 : displacement64Vol.
2B B-35INSTRUCTION FORMATS AND ENCODINGSTable B-15. General Purpose Instruction Formats and Encodingsfor 64-Bit Mode (Contd.)Instruction and FormatEncodingAL, AX, or EAX to memory0100 0000 : 1010 001w : displacementRAX to memory640100 1000 1010 0011 : displacement64MOV – Move to/from Control RegistersCR0-CR4 from register0100 0R0B : 0000 1111 : 0010 0010 : 11 eeereg (eee = CR#)CRx from qwordregister0100 1R0B : 0000 1111 : 0010 0010 : 11 eeeqwordreg (Reee = CR#)register from CR0-CR40100 0R0B : 0000 1111 : 0010 0000 : 11 eeereg (eee = CR#)qwordregister from CRx0100 1R0B 0000 1111 : 0010 0000 : 11 eeeqwordreg (Reee = CR#)MOV – Move to/from Debug RegistersDR0-DR7 from register0000 1111 : 0010 0011 : 11 eee reg (eee =DR#)DR0-DR7 from quadregister0100 10OB 0000 1111 : 0010 0011 : 11 eeereg (eee = DR#)register from DR0-DR70000 1111 : 0010 0001 : 11 eee reg (eee =DR#)quadregister from DR0-DR70100 10OB 0000 1111 : 0010 0001 : 11 eeequadreg (eee = DR#)MOV – Move to/from Segment Registersregister to segment register0100 W00Bw : 1000 1110 : 11 sreg regregister to SS0100 000B : 1000 1110 : 11 sreg regmemory to segment register0100 00XB : 1000 1110 : mod sreg r/mmemory64 to segment register (lower 16 bits) 0100 10XB 1000 1110 : mod sreg r/mmemory to SS0100 00XB : 1000 1110 : mod sreg r/msegment register to register0100 000B : 1000 1100 : 11 sreg regsegment register to qwordregister (zeroextended)0100 100B 1000 1100 : 11 sreg qwordregsegment register to memory0100 00XB : 1000 1100 : mod sreg r/msegment register to memory64 (zeroextended)0100 10XB 1000 1100 : mod sreg3 r/mB-36 Vol.
2BINSTRUCTION FORMATS AND ENCODINGSTable B-15. General Purpose Instruction Formats and Encodingsfor 64-Bit Mode (Contd.)Instruction and FormatEncodingMOVS/MOVSB/MOVSW/MOVSD/MOVSQ –Move Data from String to StringMove data from string to stringMove data from string to string (qword)1010 010w0100 1000 1010 0101MOVSX/MOVSXD – Move with Sign-Extendregister2 to register10100 0R0B : 0000 1111 : 1011 111w : 11reg1 reg2byteregister2 to qwordregister1 (signextend)0100 1R0B 0000 1111 : 1011 1110 : 11quadreg1 bytereg2wordregister2 to qwordregister10100 1R0B 0000 1111 : 1011 1111 : 11quadreg1 wordreg2dwordregister2 to qwordregister10100 1R0B 0110 0011 : 11 quadreg1dwordreg2memory to register0100 0RXB : 0000 1111 : 1011 111w : modreg r/mmemory8 to qwordregister (sign-extend)0100 1RXB 0000 1111 : 1011 1110 : modqwordreg r/mmemory16 to qwordregister0100 1RXB 0000 1111 : 1011 1111 : modqwordreg r/mmemory32 to qwordregister0100 1RXB 0110 0011 : mod qwordreg r/mMOVZX – Move with Zero-Extendregister2 to register10100 0R0B : 0000 1111 : 1011 011w : 11reg1 reg2dwordregister2 to qwordregister10100 1R0B 0000 1111 : 1011 0111 : 11qwordreg1 dwordreg2memory to register0100 0R0B : 0000 1111 : 1011 011w : modreg r/mmemory32 to qwordregister0100 1R0B 0000 1111 : 1011 0111 : modqwordreg r/mMUL – Unsigned MultiplyAL, AX, or EAX with registerRAX with qwordregister (to RDX:RAX)0100 000B : 1111 011w : 11 100 reg0100 100B 1111 0111 : 11 100 qwordregAL, AX, or EAX with memory0100 00XB 1111 011w : mod 100 r/mRAX with memory64 (to RDX:RAX)0100 10XB 1111 0111 : mod 100 r/mVol.
2B B-37INSTRUCTION FORMATS AND ENCODINGSTable B-15. General Purpose Instruction Formats and Encodingsfor 64-Bit Mode (Contd.)Instruction and FormatEncodingNEG – Two's Complement Negationregister0100 000B : 1111 011w : 11 011 regqwordregister0100 100B 1111 0111 : 11 011 qwordregmemory0100 00XB : 1111 011w : mod 011 r/mmemory640100 10XB 1111 0111 : mod 011 r/mNOP – No Operation1001 0000NOT – One's Complement Negationregister0100 000B : 1111 011w : 11 010 regqwordregister0100 000B 1111 0111 : 11 010 qwordregmemory0100 00XB : 1111 011w : mod 010 r/mmemory640100 1RXB 1111 0111 : mod 010 r/mOR – Logical Inclusive ORregister1 to register20000 100w : 11 reg1 reg2byteregister1 to byteregister20100 0R0B 0000 1000 : 11 bytereg1bytereg2qwordregister1 to qwordregister20100 1R0B 0000 1001 : 11 qwordreg1qwordreg2register2 to register10000 101w : 11 reg1 reg2byteregister2 to byteregister10100 0R0B 0000 1010 : 11 bytereg1bytereg2qwordregister2 to qwordregister10100 0R0B 0000 1011 : 11 qwordreg1qwordreg2memory to register0000 101w : mod reg r/mmemory8 to byteregister0100 0RXB 0000 1010 : mod bytereg r/mmemory8 to qwordregister0100 0RXB 0000 1011 : mod qwordreg r/mregister to memory0000 100w : mod reg r/mbyteregister to memory80100 0RXB 0000 1000 : mod bytereg r/mqwordregister to memory640100 1RXB 0000 1001 : mod qwordreg r/mimmediate to register1000 00sw : 11 001 reg : immimmediate8 to byteregister0100 000B 1000 0000 : 11 001 bytereg :imm8B-38 Vol.
2BINSTRUCTION FORMATS AND ENCODINGSTable B-15. General Purpose Instruction Formats and Encodingsfor 64-Bit Mode (Contd.)Instruction and FormatEncodingimmediate32 to qwordregister0100 000B 1000 0001 : 11 001 qwordreg :imm32immediate8 to qwordregister0100 000B 1000 0011 : 11 001 qwordreg :imm8immediate to AL, AX, or EAX0000 110w : immimmediate64 to RAX0100 1000 0000 1101 : imm64immediate to memory1000 00sw : mod 001 r/m : immimmediate8 to memory80100 00XB 1000 0000 : mod 001 r/m : imm8immediate32 to memory640100 00XB 1000 0001 : mod 001 r/m : imm32immediate8 to memory640100 00XB 1000 0011 : mod 001 r/m : imm8OUT – Output to Portfixed port1110 011w : port numbervariable port1110 111wOUTS – Output to DX Portoutput to DX Port0110 111wPOP – Pop a Value from the Stackwordregister0101 0101 : 0100 000B : 1000 1111 : 11 000reg16qwordregister0100 W00BS : 1000 1111 : 11 000 reg64wordregister (alternate encoding)0101 0101 : 0100 000B : 0101 1 reg16qwordregister (alternate encoding)0100 W00B : 0101 1 reg64memory640100 W0XBS : 1000 1111 : mod 000 r/mmemory160101 0101 : 0100 00XB 1000 1111 : mod000 r/mPOP – Pop a Segment Register from the Stack(Note: CS cannot be sreg2 in this usage.)segment register FS, GS0000 1111: 10 sreg3 001POPF/POPFQ – Pop Stack into FLAGS/RFLAGSRegisterpop stack to FLAGS register0101 0101 : 1001 1101pop Stack to RFLAGS register0100 1000 1001 1101PUSH – Push Operand onto the StackVol.
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