Volume 2B Instruction Set Reference N-Z (794102), страница 66
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Do not depend on the operation of undefined or reserved locations.Table A-22 shows the opcode map if the ModR/M byte is outside the range of00H-BFH. The first digit of the ModR/M byte selects the table row and the seconddigit selects the column.Table A-22. DF Opcode Map When ModR/M Byte is Outside 00H to BFH *01234567ST(0),ST(0)ST(0),ST(1)ST(0),ST(2)ST(0),ST(3)ST(0),ST(4)ST(0),ST(5)ST(0),ST(6)ST(0),ST(7)89ABCDEFST(0),ST(4)ST(0),ST(5)ST(0),ST(6)ST(0),ST(7)CDEFSTSWAXFFCOMIPCDEFUCOMIPST(0),ST(0)ST(0),ST(1)ST(0),ST(2)ST(0),ST(3)FNOTES:* All blanks in all opcode maps are reserved and must not be used.
Do not depend on the operation of undefined or reserved locations.Vol. 2B A-31OPCODE MAPA-32 Vol. 2BAPPENDIX BINSTRUCTION FORMATS AND ENCODINGSThis appendix provides machine instruction formats and encodings of IA-32 instructions. The first section describes the IA-32 architecture’s machine instruction format.The remaining sections show the formats and encoding of general-purpose, MMX, P6family, SSE/SSE2/SSE3, x87 FPU instructions, and VMX instructions.
Those instruction formats also apply to Intel 64 architecture. Instruction formats used in 64-bitmode are provided as supersets of the above.B.1MACHINE INSTRUCTION FORMATAll Intel Architecture instructions are encoded using subsets of the general machineinstruction format shown in Figure B-1. Each instruction consists of:••an opcode•a displacement and an immediate data field (if required)a register and/or address mode specifier consisting of the ModR/M byte andsometimes the scale-index-base (SIB) byte (if required)Legacy PrefixesREX Prefixes765432107654321076543210TTTTTTTTTTTTTTTTTTTTTTTTGrp 1, Grp 2, (optional)Grp 3, Grp 47-65-32-0Mod Reg* R/MModR/M Byte7-61, 2, or 3 Byte Opcodes (T = Opcode5-32-0Scale Index BaseSIB ByteRegister and/or AddressMode Specifierd32 | 16 | 8 | Noned32 | 16 | 8 | NoneAddress DisplacementImmediate Data(4, 2, 1 Bytes or None) (4,2,1 Bytes or None)NOTE:* The Reg Field may be used as anFigure B-1.
General Machine Instruction FormatThe following sections discuss this format.Vol. 2B B-1INSTRUCTION FORMATS AND ENCODINGSB.1.1Legacy PrefixesThe legacy prefixes noted in Figure B-1 include 66H, 67H, F2H and F3H. They areoptional, except when F2H, F3H and 66H are used in new instruction extensions.Legacy prefixes must be placed before REX prefixes.Refer to Chapter 2, “Instruction Format,” in the Intel® 64 and IA-32 ArchitecturesSoftware Developer’s Manual, Volume 2A, for more information on legacy prefixes.B.1.2REX PrefixesREX prefixes are a set of 16 opcodes that span one row of the opcode map andoccupy entries 40H to 4FH.
These opcodes represent valid instructions (INC or DEC)in IA-32 operating modes and in compatibility mode. In 64-bit mode, the sameopcodes represent the instruction prefix REX and are not treated as individualinstructions.Refer to Chapter 2, “Instruction Format,” in the Intel® 64 and IA-32 ArchitecturesSoftware Developer’s Manual, Volume 2A, for more information on REX prefixes.B.1.3Opcode FieldsThe primary opcode for an instruction is encoded in one to three bytes of the instruction.
Within the primary opcode, smaller encoding fields may be defined. These fieldsvary according to the class of operation being performed.Almost all instructions that refer to a register and/or memory operand have aregister and/or address mode byte following the opcode. This byte, the ModR/M byte,consists of the mod field (3 bits), the reg field (3 bits; this field is sometimes anopcode extension), and the R/M field (2 bits).
Certain encodings of the ModR/M byteindicate that a second address mode byte, the SIB byte, must be used.If the addressing mode specifies a displacement, the displacement value is placedimmediately following the ModR/M byte or SIB byte. Possible sizes are 8, 16, or 32bits. If the instruction specifies an immediate value, the immediate value follows anydisplacement bytes. The immediate, if specified, is always the last field of the instruction.Refer to Chapter 2, “Instruction Format,” in the Intel® 64 and IA-32 ArchitecturesSoftware Developer’s Manual, Volume 2A, for more information on opcodes.B.1.4Special FieldsTable B-1 lists bit fields that appear in certain instructions, sometimes within theopcode bytes.
All of these fields (except the d bit) occur in the general-purposeinstruction formats in Table B-13.B-2 Vol. 2BINSTRUCTION FORMATS AND ENCODINGSTable B-1. Special Fields Within Instruction EncodingsField NameNumber ofBitsDescriptionregGeneral-register specifier (see Table B-4 or B-5)3wSpecifies if data is byte or full-sized, where full-sized is 16 or 32bits (see Table B-6)1sSpecifies sign extension of an immediate field (see Table B-7)1sreg2Segment register specifier for CS, SS, DS, ES (see Table B-8)2sreg3Segment register specifier for CS, SS, DS, ES, FS, GS (see Table B-8)3eeeSpecifies a special-purpose (control or debug) register (seeTable B-9)3tttnFor conditional instructions, specifies a condition asserted ornegated (see Table B-12)4Specifies direction of data operation (see Table B-11)1dB.1.4.1Reg Field (reg) for Non-64-Bit ModesThe reg field in the ModR/M byte specifies a general-purpose register operand. Thegroup of registers specified is modified by the presence and state of the w bit in anencoding (refer to Section B.1.4.3).
Table B-2 shows the encoding of the reg fieldwhen the w bit is not present in an encoding; Table B-3 shows the encoding of the regfield when the w bit is present.Table B-2. Encoding of reg Field When w Field is Not Present in Instructionreg FieldRegister Selected during16-Bit Data OperationsRegister Selected during32-Bit Data Operations000AXEAX001CXECX010DXEDX011BXEBX100SPESP101BPEBP110SIESI111DIEDIVol. 2B B-3INSTRUCTION FORMATS AND ENCODINGSTable B-3. Encoding of reg Field When w Field is Present in InstructionRegister Specified by reg FieldDuring 16-Bit Data OperationsRegister Specified by reg FieldDuring 32-Bit Data OperationsFunction of w FieldFunction of w FieldregWhen w = 0When w = 1regWhen w = 0When w = 1000ALAX000ALEAX001CLCX001CLECX010DLDX010DLEDX011BLBX011BLEBX100AHSP100AHESP101CHBP101CHEBP110DHSI110DHESI111BHDI111BHEDIB.1.4.2Reg Field (reg) for 64-Bit ModeJust like in non-64-bit modes, the reg field in the ModR/M byte specifies a generalpurpose register operand.
The group of registers specified is modified by the presence of and state of the w bit in an encoding (refer to Section B.1.4.3). Table B-4shows the encoding of the reg field when the w bit is not present in an encoding;Table B-5 shows the encoding of the reg field when the w bit is present.Table B-4. Encoding of reg Field When w Field is Not Present in Instructionreg FieldRegister Selectedduring16-Bit Data OperationsRegister Selectedduring32-Bit Data OperationsRegister Selectedduring64-Bit Data Operations000AXEAXRAX001CXECXRCX010DXEDXRDX011BXEBXRBX100SPESPRSP101BPEBPRBP110SIESIRSI111DIEDIRDIB-4 Vol.
2BINSTRUCTION FORMATS AND ENCODINGSTable B-5. Encoding of reg Field When w Field is Present in InstructionRegister Specified by reg FieldDuring 16-Bit Data OperationsRegister Specified by reg FieldDuring 32-Bit Data OperationsFunction of w FieldFunction of w FieldregWhen w = 0When w = 1regWhen w = 0When w = 1000ALAX000ALEAX001CLCX001CLECX010DLDX010DLEDX011BLBX011BLEBX100AH1SP100AH*ESP101CH1BP101CH*EBP110DH1SI110DH*ESI111BH1DI111BH*EDINOTES:1. AH, CH, DH, BH can not be encoded when REX prefix is used. Such an expression defaults to thelow byte.B.1.4.3Encoding of Operand Size (w) BitThe current operand-size attribute determines whether the processor is performing16-bit, 32-bit or 64-bit operations.
Within the constraints of the current operand-sizeattribute, the operand-size bit (w) can be used to indicate operations on 8-bit operands or the full operand size specified with the operand-size attribute. Table B-6shows the encoding of the w bit depending on the current operand-size attribute.Table B-6. Encoding of Operand Size (w) Bitw BitOperand Size WhenOperand-Size Attribute is 16 BitsOperand Size WhenOperand-Size Attribute is 32 Bits08 Bits8 Bits116 Bits32 BitsB.1.4.4Sign-Extend (s) BitThe sign-extend (s) bit occurs in instructions with immediate data fields that arebeing extended from 8 bits to 16 or 32 bits. See Table B-7.Vol.
2B B-5INSTRUCTION FORMATS AND ENCODINGSTable B-7. Encoding of Sign-Extend (s) BitEffect on 8-BitImmediate DatasEffect on 16- or 32-BitImmediate Data0NoneNone1Sign-extend to fill 16-bit or 32-bit destinationNoneB.1.4.5Segment Register (sreg) FieldWhen an instruction operates on a segment register, the reg field in the ModR/M byteis called the sreg field and is used to specify the segment register. Table B-8 showsthe encoding of the sreg field. This field is sometimes a 2-bit field (sreg2) and othertimes a 3-bit field (sreg3).Table B-8.
Encoding of the Segment Register (sreg) Field2-Bit sreg2 FieldSegment RegisterSelected3-Bit sreg3 FieldSegment RegisterSelected00ES000ES01CS001CS10SS010SS11DS011DS100FS101GS110Reserved1111ReservedNOTES:1. Do not use reserved encodings.B.1.4.6Special-Purpose Register (eee) FieldWhen control or debug registers are referenced in an instruction they are encoded inthe eee field, located in bits 5 though 3 of the ModR/M byte (an alternate encoding ofthe sreg field).
See Table B-9.B-6 Vol. 2BINSTRUCTION FORMATS AND ENCODINGSTable B-9. Encoding of Special-Purpose Register (eee) FieldeeeControl RegisterDebug Register000CR0DR01001ReservedDR1010CR2DR2011CR3DR3100CR4Reserved101ReservedReserved110ReservedDR6111ReservedDR7NOTES:1. Do not use reserved encodings.B.1.4.7Condition Test (tttn) FieldFor conditional instructions (such as conditional jumps and set on condition), thecondition test field (tttn) is encoded for the condition being tested.
The ttt part of thefield gives the condition to test and the n part indicates whether to use the condition(n = 0) or its negation (n = 1).•For 1-byte primary opcodes, the tttn field is located in bits 3, 2, 1, and 0 of theopcode byte.•For 2-byte primary opcodes, the tttn field is located in bits 3, 2, 1, and 0 of thesecond opcode byte.Table B-10 shows the encoding of the tttn field.Vol. 2B B-7INSTRUCTION FORMATS AND ENCODINGSTable B-10. Encoding of Conditional Test (tttn) FieldtttnMnemonic0000B.1.4.8ConditionOOverflow0001NONo overflow0010B, NAEBelow, Not above or equal0011NB, AENot below, Above or equal0100E, ZEqual, Zero0101NE, NZNot equal, Not zero0110BE, NABelow or equal, Not above0111NBE, ANot below or equal, Above1000SSign1001NSNot sign1010P, PEParity, Parity Even1011NP, PONot parity, Parity Odd1100L, NGELess than, Not greater than or equal to1101NL, GENot less than, Greater than or equal to1110LE, NGLess than or equal to, Not greater than1111NLE, GNot less than or equal to, Greater thanDirection (d) BitIn many two-operand instructions, a direction bit (d) indicates which operand isconsidered the source and which is the destination.
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