Volume 2B Instruction Set Reference N-Z (794102), страница 62
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Blank cells in the tablesindicate opcodes that are reserved or undefined.The opcode map tables are organized by hex values of the upper and lower 4 bits ofan opcode byte. For 1-byte encodings (Table A-2), use the four high-order bits of anopcode to index a row of the opcode table; use the four low-order bits to index acolumn of the table. For 2-byte opcodes beginning with 0FH (Table A-3), skip anyinstruction prefixes, the 0FH byte (0FH may be preceded by 66H, F2H, or F3H) anduse the upper and lower 4-bit values of the next opcode byte to index table rows andcolumns. Similarly, for 3-byte opcodes beginning with 0F38H or 0F3AH (Table A-4),skip any instruction prefixes, 0F38H or 0F3AH and use the upper and lower 4-bitvalues of the third opcode byte to index table rows and columns.
See Section A.2.4,“Opcode Look-up Examples for One, Two, and Three-Byte Opcodes.”When a ModR/M byte provides opcode extensions, this information qualifies opcodeexecution. For information on how an opcode extension in the ModR/M byte modifiesthe opcode map in Table A-2 and Table A-3, see Section A.4.The escape (ESC) opcode tables for floating point instructions identify the eight highorder bits of opcodes at the top of each page.
See Section A.5. If the accompanyingModR/M byte is in the range of 00H-BFH, bits 3-5 (the top row of the third table oneach page) along with the reg bits of ModR/M determine the opcode. ModR/M bytesoutside the range of 00H-BFH are mapped by the bottom two tables on each page ofthe section.Vol. 2B A-1OPCODE MAPA.2KEY TO ABBREVIATIONSOperands are identified by a two-character code of the form Zz. The first character,an uppercase letter, specifies the addressing method; the second character, a lowercase letter, specifies the type of operand.A.2.1Codes for Addressing MethodThe following abbreviations are used to document addressing methods:ADirect address: the instruction has no ModR/M byte; the address of theoperand is encoded in the instruction.
No base register, index register, orscaling factor can be applied (for example, far JMP (EA)).CThe reg field of the ModR/M byte selects a control register (for example, MOV(0F20, 0F22)).DThe reg field of the ModR/M byte selects a debug register (for example,MOV (0F21,0F23)).EA ModR/M byte follows the opcode and specifies the operand.
The operand iseither a general-purpose register or a memory address. If it is a memoryaddress, the address is computed from a segment register and any of thefollowing values: a base register, an index register, a scaling factor, adisplacement.FEFLAGS/RFLAGS Register.GThe reg field of the ModR/M byte selects a general register (for example, AX(000)).IImmediate data: the operand value is encoded in subsequent bytes of theinstruction.JThe instruction contains a relative offset to be added to the instructionpointer register (for example, JMP (0E9), LOOP).MThe ModR/M byte may refer only to memory (for example, BOUND, LES,LDS, LSS, LFS, LGS, CMPXCHG8B).NThe R/M field of the ModR/M byte selects a packed-quadword, MMX technology register.OThe instruction has no ModR/M byte.
The offset of the operand is coded as aword or double word (depending on address size attribute) in the instruction.No base register, index register, or scaling factor can be applied (for example,MOV (A0–A3)).PThe reg field of the ModR/M byte selects a packed quadword MMX technologyregister.QA ModR/M byte follows the opcode and specifies the operand. The operand iseither an MMX technology register or a memory address. If it is a memoryaddress, the address is computed from a segment register and any of theA-2 Vol. 2BOPCODE MAPfollowing values: a base register, an index register, a scaling factor, and adisplacement.RThe R/M field of the ModR/M byte may refer only to a general register (forexample, MOV (0F20-0F23)).SThe reg field of the ModR/M byte selects a segment register (for example,MOV (8C,8E)).UThe R/M field of the ModR/M byte selects a 128-bit XMM register.VThe reg field of the ModR/M byte selects a 128-bit XMM register.WA ModR/M byte follows the opcode and specifies the operand.
The operand iseither a 128-bit XMM register or a memory address. If it is a memoryaddress, the address is computed from a segment register and any of thefollowing values: a base register, an index register, a scaling factor, and adisplacement.XMemory addressed by the DS:rSI register pair (for example, MOVS, CMPS,OUTS, or LODS).YMemory addressed by the ES:rDI register pair (for example, MOVS, CMPS,INS, STOS, or SCAS).A.2.2Codes for Operand TypeThe following abbreviations are used to document operand types:aTwo one-word operands in memory or two double-word operands in memory,depending on operand-size attribute (used only by the BOUND instruction).bByte, regardless of operand-size attribute.cByte or word, depending on operand-size attribute.dDoubleword, regardless of operand-size attribute.dqDouble-quadword, regardless of operand-size attribute.p32-bit or 48-bit pointer, depending on operand-size attribute.piQuadword MMX technology register (for example: mm0).ps128-bit packed single-precision floating-point data.qQuadword, regardless of operand-size attribute.s6-byte or 10-byte pseudo-descriptor.ssScalar element of a 128-bit packed single-precision floating data.siDoubleword integer register (for example: eax).vWord, doubleword or quadword (in 64-bit mode), depending on operand-sizeattribute.wWord, regardless of operand-size attribute.zWord for 16-bit operand-size or doubleword for 32 or 64-bit operand-size.Vol.
2B A-3OPCODE MAPA.2.3Register CodesWhen an opcode requires a specific register as an operand, the register is identifiedby name (for example, AX, CL, or ESI). The name indicates whether the register is64, 32, 16, or 8 bits wide.A register identifier of the form eXX or rXX is used when register width depends onthe operand-size attribute.
eXX is used when 16 or 32-bit sizes are possible; rXX isused when 16, 32, or 64-bit sizes are possible. For example: eAX indicates that theAX register is used when the operand-size attribute is 16 and the EAX register is usedwhen the operand-size attribute is 32. rAX can indicate AX, EAX or RAX.When the REX.B bit is used to modify the register specified in the reg field of theopcode, this fact is indicated by adding “/x” to the register name to indicate the additional possibility. For example, rCX/r9 is used to indicate that the register could eitherbe rCX or r9.
Note that the size of r9 in this case is determined by the operand sizeattribute (just as for rCX).A.2.4Opcode Look-up Examples for One, Two,and Three-Byte OpcodesThis section provides examples that demonstrate how opcode maps are used.A.2.4.1One-Byte Opcode InstructionsThe opcode map for 1-byte opcodes is shown in Table A-2. The opcode map for1-byte opcodes is arranged by row (the least-significant 4 bits of the hexadecimalvalue) and column (the most-significant 4 bits of the hexadecimal value). Each entryin the table lists one of the following types of opcodes:•Instruction mnemonics and operand types using the notations listed in SectionA.2•Opcodes used as an instruction prefixFor each entry in the opcode map that corresponds to an instruction, the rules forinterpreting the byte following the primary opcode fall into one of the followingcases:•A ModR/M byte is required and is interpreted according to the abbreviations listedin Section A.1 and Chapter 2, “Instruction Format,” of the Intel® 64 and IA-32Architectures Software Developer’s Manual, Volume 2A.
Operand types are listedaccording to notations listed in Section A.2.•A ModR/M byte is required and includes an opcode extension in the reg field inthe ModR/M byte. Use Table A-6 when interpreting the ModR/M byte.•Use of the ModR/M byte is reserved or undefined. This applies to entries thatrepresent an instruction prefix or entries for instructions without operands thatuse ModR/M (for example: 60H, PUSHA; 06H, PUSH ES).A-4 Vol. 2BOPCODE MAPExample A-1. Look-up Example for 1-Byte OpcodesOpcode 030500000000H for an ADD instruction is interpreted using the 1-byteopcode map (Table A-2) as follows:•The first digit (0) of the opcode indicates the table row and the second digit (3)indicates the table column. This locates an opcode for ADD with two operands.•The first operand (type Gv) indicates a general register that is a word ordoubleword depending on the operand-size attribute.
The second operand (typeEv) indicates a ModR/M byte follows that specifies whether the operand is a wordor doubleword general-purpose register or a memory address.•The ModR/M byte for this instruction is 05H, indicating that a 32-bit displacementfollows (00000000H). The reg/opcode portion of the ModR/M byte (bits 3-5) is000, indicating the EAX register.The instruction for this opcode is ADD EAX, mem_op, and the offset of mem_op is00000000H.Some 1- and 2-byte opcodes point to group numbers (shaded entries in the opcodemap table).
Group numbers indicate that the instruction uses the reg/opcode bits inthe ModR/M byte as an opcode extension (refer to Section A.4).A.2.4.2Two-Byte Opcode InstructionsThe two-byte opcode map shown in Table A-3 includes primary opcodes that areeither two bytes or three bytes in length. Primary opcodes that are 2 bytes in lengthbegin with an escape opcode 0FH. The upper and lower four bits of the secondopcode byte are used to index a particular row and column in Table A-3.Two-byte opcodes that are 3 bytes in length begin with a mandatory prefix (66H,F2H, or F3H) and the escape opcode (OFH). The upper and lower four bits of the thirdbyte are used to index a particular row and column in Table A-3 (except when thesecond opcode byte is the 3-byte escape opcodes 38H or 3AH; in this situation referto Section A.2.4.3).For each entry in the opcode map, the rules for interpreting the byte following theprimary opcode fall into one of the following cases:•A ModR/M byte is required and is interpreted according to the abbreviations listedin Section A.1 and Chapter 2, “Instruction Format,” of the Intel® 64 and IA-32Architectures Software Developer’s Manual, Volume 2A.
The operand types arelisted according to notations listed in Section A.2.•A ModR/M byte is required and includes an opcode extension in the reg field inthe ModR/M byte. Use Table A-6 when interpreting the ModR/M byte.•Use of the ModR/M byte is reserved or undefined. This applies to entries thatrepresent an instruction without operands that are encoded using ModR/M (forexample: 0F77H, EMMS).Vol. 2B A-5OPCODE MAPExample A-2. Look-up Example for 2-Byte OpcodesLook-up opcode 0FA4050000000003H for a SHLD instruction using Table A-3.•The opcode is located in row A, column 4.
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