Volume 2B Instruction Set Reference N-Z (794102), страница 63
Текст из файла (страница 63)
The location indicates a SHLDinstruction with operands Ev, Gv, and Ib. Interpret the operands as follows:— Ev: The ModR/M byte follows the opcode to specify a word or doublewordoperand.— Gv: The reg field of the ModR/M byte selects a general-purpose register.— Ib: Immediate data is encoded in the subsequent byte of the instruction.•The third byte is the ModR/M byte (05H).
The mod and opcode/reg fields ofModR/M indicate that a 32-bit displacement is used to locate the first operand inmemory and eAX as the second operand.•The next part of the opcode is the 32-bit displacement for the destinationmemory operand (00000000H). The last byte stores immediate byte thatprovides the count of the shift (03H).•By this breakdown, it has been shown that this opcode represents theinstruction: SHLD DS:00000000H, EAX, 3.A.2.4.3Three-Byte Opcode InstructionsThe three-byte opcode maps shown in Table A-4 and Table A-5 includes primaryopcodes that are either 3 or 4 bytes in length. Primary opcodes that are 3 bytes inlength begin with two escape bytes 0F38H or 0F3A. The upper and lower four bits ofthe third opcode byte are used to index a particular row and column in Table A-4 orTable A-5.Three-byte opcodes that are 4 bytes in length begin with a mandatory prefix (66H,F2H, or F3H) and two escape bytes (0F38H or 0F3AH).
The upper and lower four bitsof the fourth byte are used to index a particular row and column in Table A-4 orTable A-5.For each entry in the opcode map, the rules for interpreting the byte following theprimary opcode fall into the following case:•A ModR/M byte is required and is interpreted according to the abbreviations listedin Section A.1 and Chapter 2, “Instruction Format,” of the Intel® 64 and IA-32Architectures Software Developer’s Manual, Volume 2A.
The operand types arelisted according to notations listed in Section A.2.Example A-3. Look-up Example for 3-Byte OpcodesLook-up opcode 660F3A0FC108H for a PALIGNR instruction using Table A-5.•66H is a prefix and 0F3AH indicate to use Table A-5. The opcode is located in row0, column F indicating a PALIGNR instruction with operands Vdq, Wdq, and Ib.Interpret the operands as follows:— Vdq: The reg field of the ModR/M byte selects a 128-bit XMM register.A-6 Vol. 2BOPCODE MAP— Wdq: The R/M field of the ModR/M byte selects either a 128-bit XMM registeror memory location.— Ib: Immediate data is encoded in the subsequent byte of the instruction.•The next byte is the ModR/M byte (C1H). The reg field indicates that the firstoperand is XMM0. The mod shows that the R/M field specifies a register and theR/M indicates that the second operand is XMM1.••The last byte is the immediate byte (08H).By this breakdown, it has been shown that this opcode represents theinstruction: PALIGNR XMM0, XMM1, 8.A.2.5Superscripts Utilized in Opcode TablesTable A-1 contains notes on particular encodings.
These notes are indicated in thefollowing opcode maps by superscripts.Table A-1. Superscripts Utilized in Opcode TablesSuperscriptSymbolMeaning of Symbol1ABits 5, 4, and 3 of ModR/M byte used as an opcode extension (refer to SectionA.4, “Opcode Extensions For One-Byte And Two-byte Opcodes”).1BUse the 0F0B opcode (UD2 instruction) or the 0FB9H opcode when deliberatelytrying to generate an invalid opcode exception (#UD).1CSome instructions added in the Pentium III processor may use the same twobyte opcode. If the instruction has variations, or the opcode represents differentinstructions, the ModR/M byte will be used to differentiate the instruction.
Forthe value of the ModR/M byte needed to decode the instruction, see Table A-6.These instructions include SFENCE, STMXCSR, LDMXCSR, FXRSTOR, andFXSAVE, as well as PREFETCH and its variations.i64The instruction is invalid or not encodable in 64-bit mode. 40 through 4F (singlebyte INC and DEC) are REX prefix combinations when in 64-bit mode (use FE/FFGrp 4 and 5 for INC and DEC).o64Instruction is only available when in 64-bit mode.d64When in 64-bit mode, instruction defaults to 64-bit operand size and cannotencode 32-bit operand size.f64The operand size is forced to a 64-bit operand size when in 64-bit mode(prefixes that change operand size are ignored for this instruction in 64-bitmode).Vol.
2B A-7OPCODE MAPA.3ONE, TWO, AND THREE-BYTE OPCODE MAPSSee Table A-2 through Table A-5 below. The tables are multiple page presentations.Rows and columns with sequential relationships are placed on facing pages to makelook-up tasks easier. Note that table footnotes are not presented on each page. Tablefootnotes for each table are presented on the last page of the table. Gray cells indicate instruction groupings.A-8 Vol.
2BThisepagtentinionallyleftblank.OPCODE MAPVol. 2B A-9OPCODE MAPTable A-2. One-byte Opcode Map: (00H — F7H) *01230Eb, GbEv, GvGb, EbEb, GbEv, GvGb, EbEb, GbEv, GvGb, Eb15Gv, EvAL, IbrAX, IzGv, EvAL, IbrAX, IzGv, EvAL, IbrAX, IzADC2AND3XOREb, GbEv, GvGb, EbGv, EvAL, IbrAX, Iz67PUSHESi64POPESi64PUSHSSi64POPSSi64SEG=ES(Prefix)DAAi64SEG=SS(Prefix)AAAi64eSIREX.RXeDIREX.RXBINCi64 general register / REXo64 Prefixes4eAXREXeCXREX.BeDXREX.XeBXREX.XBeSPREX.ReBPREX.RBPUSHd64 general register564ADDrAX/r8rCX/r9rDX/r10rBX/r11rSP/r12rBP/r13rSI/r14rDI/r15PUSHAi64/PUSHADi64POPAi64/POPADi64BOUNDi64Gv, MaARPLi64Ew, GwSEG=FS(Prefix)SEG=GS(Prefix)OperandSize(Prefix)AddressSize(Prefix)MOVSXDo64Gv, EvJccf64, Jb - Short-displacement jump on condition7ONOEb, Ib9B/NAE/CNOPPAUSE(F3)XCHG r8, rAXEv, IbrCX/r9rDX/r10rBX/r11MOVAL, ObNZ/NEBE/NAEb, GbNBE/AXCHGEv, GvEb, GbEv, GvXCHG word, double-word or quad-word register with rAXrAX, OvOb, ALBOv, rAXrSP/r12rBP/r13rSI/r14rDI/r15MOVS/BXb, YbMOVS/W/D/QXv, YvCMPS/BXb, YbCMPS/W/DXv, YvDH/R14L, IbBH/R15L, IbMOV immediate byte into byte registerAL/R8L, IbCL/R9L, IbShift Grp 21ACEb, IbEv, IbDL/R10L, IbBL/R11L, IbAH/R12L, IbCH/R13L, IbRETNf64IwRETNf64LESi64Gz, MpLDSi64Gz, MpAAMi64IbAADi64IbShift Grp 21ADFZ/ETESTEb, Ibi64Ev, IzAENB/AE/NCImmediate Grp 11A8Eb, 1Ev, 1Eb, CLEv, CLLOOPNEf64/LOOPNZf64JbLOOPEf64/LOOPZf64JbLOOPf64JbJrCXZf64/JbREPNE(Prefix)REP/REPE(Prefix)LOCK(Prefix)A-10 Vol.
2BGrp 111A - MOVEb, IbEv, IzXLAT/XLATBINOUTAL, IbeAX, IbHLTCMCIb, ALIb, eAXUnary Grp 31AEbEvOPCODE MAPTable A-2. One-byte Opcode Map: (08H — FFH) *89AB0Eb, GbEv, GvGb, EbEb, GbEv, GvGb, EbEb, GbEv, GvGb, EbEb, GbEv, GvGb, Eb1AL, IbrAX, IzGv, EvAL, IbrAX, IzPUSHDSi64POPDSi64Gv, EvAL, IbrAX, IzSEG=CS(Prefix)DASi64Gv, EvAL, IbrAX, IzSEG=DS(Prefix)AASi64eSIREX.WRXeDIREX.WRXBeAXREX.WeCXREX.WBeDXREX.WXrAX/r8rCX/r9rDX/r10eBXREX.WXBeSPREX.WReBPREX.WRBrBX/r11rSP/r12rBP/r13rSI/r14rDI/r15PUSHd64IzIMULGv, Ev, IzPUSHd64IbIMULGv, Ev, IbINS/INSBYb, DXINS/INSW/INSDYz, DXOUTS/OUTSBDX, XbOUTS/OUTSW/OUTSDDX, XzSNSP/PEPOPd64 into general registerJccf64, Jb- Short displacement jump on condition78NP/POMOVL/NGENL/GELE/NGNLE/GMOVEv, SwLEAGv, MMOVSw, EwGrp 1A1APOPd64 EvEb, GbEv, GvGb, EbGv, EvCBW/CWDE/CDQECWD/CDQ/CQOCALLFi64ApFWAIT/WAITPUSHF/D/Qd64/FvPOPF/D/Qd64/FvSAHFLAHFSTOS/BYb, ALSTOS/W/D/QYv, rAXLODS/BAL, XbLODS/W/D/QrAX, XvSCAS/BAL, YbSCAS/W/D/QrAX, XvATESTAL, IbrAX, IzrAX/r8, IvrCX/r9, IvrDX/r10, IvrBX/r11, IvrSP/r12, IvrBP/r13, IvrSI/r14, IvrDI/r15 , IvENTERLEAVEd64RETFRETFINT 3INTINTOi64IRET/D/QBMOV immediate word or double into word, double, or quad registerIw, IbIwDFGv, EvDECi64 general register / REXo64 Prefixes5EF2-byteescape(Table A-3)CMP4CEPUSHCSi64SUB39DSBB26CORIbESC (Escape to coprocessor instruction set)CALLf64JMPINOUTJznearf64Jzfari64APshortf64JbAL, DXeAX, DXDX, ALDX, eAXCLCSTCCLISTICLDSTDINC/DECINC/DECGrp 41AGrp 51ANOTES:* All blanks in all opcode maps are reserved and must not be used.
Do not depend on the operation of undefined or reserved locations.Vol. 2B A-11OPCODE MAPTable A-3. Two-byte Opcode Map: 00H — 77H (First Byte is 0FH) *01230Grp 61AGrp 71ALARGv, EwLSLGv, Ew1movupsVps, Wpsmovss (F3)Vss, Wssmovupd (66)Vpd, Wpdmovsd (F2)Vsd, WsdmovupsWps, Vpsmovss (F3)Wss, Vssmovupd (66)Wpd, Vpdmovsd (F2)Vsd, WsdmovlpsVq, Mqmovlpd (66)Vq, MqmovhlpsVq, Uqmovddup(F2)Vq, Wqmovsldup(F3)Vq, WqmovlpsMq, Vqmovlpd (66)Mq, Vq2MOVRd, CdMOVRd, DdMOVCd, RdMOVDd, Rd3WRMSRRDTSCRDMSRRDPMCONOB/C/NAEAE/NB/NCE/Z5movmskpsGd, Upsmovmskpd(66)Gd, UpdsqrtpsVps, Wpssqrtss (F3)Vss, Wsssqrtpd (66)Vpd, Wpdsqrtsd (F2)Vsd, WsdrsqrtpsVps, Wpsrsqrtss (F3)Vss, WssrcppsVps, Wpsrcpss (F3)Vss, WssandpsVps, Wpsandpd (66)Vpd, Wpd6punpcklbwPq, Qdpunpcklbw(66)Vdq, WdqpunpcklwdPq, Qdpunpcklwd(66)Vdq, WdqpcmpgtbPq, Qqpcmpgtb (66)Vdq, Wdq7pshufwPq, Qq, Ibpshufd (66)Vdq,Wdq,Ibpshufhw(F3)Vdq,Wdq,Ibpshuflw (F2)Vdq Wdq,Ib(Grp 121A)pcmpeqbPq, Qqpcmpeqb (66)Vdq, Wdq44567SYSCALLo64CLTSSYSRETo64unpcklpsVps, Wqunpcklpd (66)Vpd, WqunpckhpsVps, Wqunpckhpd (66)Vpd, WqmovhpsVq, Mqmovhpd (66)Vq, MqmovlhpsVq, Uqmovshdup(F3)Vq, WqmovhpsMq, Vqmovhpd(66)Mq, VqSYSENTERSYSEXITNE/NZBE/NAA/NBEandnpsVps, Wpsandnpd (66)Vpd, WpdorpsVps, Wpsorpd (66)Vpd, WpdxorpsVps, Wpsxorpd (66)Vpd, WpdpcmpgtwPq, Qqpcmpgtw (66)Vdq, WdqpcmpgtdPq, Qqpcmpgtd (66)Vdq, WdqpackuswbPq, Qqpackuswb (66)Vdq, WdqpcmpeqwPq, Qqpcmpeqw (66)Vdq, WdqpcmpeqdPq, Qqpcmpeqd (66)Vdq, WdqemmsCMOVcc, (Gv, Ev) - Conditional MoveA-12 Vol.
2BpunpckldqpacksswbPq, QdPq, Qqpunpckldq (66) packsswb (66)Vdq, WdqVdq, Wdq(Grp 131A)(Grp 141A)OPCODE MAPTable A-3. Two-byte Opcode Map: 08H — 7FH (First Byte is 0FH) *890INVDWBINVD1Prefetch1C(Grp 161A)2movapsVps, Wpsmovapd (66)Vpd, Wpd33-byte escape(Table A-4)ABCDEFNOP Ev2-byte IllegalOpcodesUD21BNOP EvmovapsWps, Vpsmovapd (66)Wpd, Vpdcvtpi2psVps, Qqcvtsi2ss (F3)Vss, Ed/qcvtpi2pd (66)Vpd, Qqcvtsi2sd (F2)Vsd, Ed/qmovntpsMps, Vpsmovntpd (66)Mpd, Vpdcvttps2piQq, Wpscvttss2si (F3)Gd, Wsscvttpd2pi (66)Qdq, Wpdcvttsd2si (F2)Gd, Wsdcvtps2piQq, Wpscvtss2si (F3)Gd/q, Wsscvtpd2pi (66)Qdq, Wpdcvtsd2si (F2)Gd/q, WsducomissVss, Wssucomisd (66)Vsd, WsdcomissVps, Wpscomisd (66)Vsd, Wsd3-byte escape(Table A-5)4CMOVcc(Gv, Ev) - Conditional MoveSNS5addpsVps, Wpsaddss (F3)Vss, Wssaddpd (66)Vpd, Wpdaddsd (F2)Vsd, WsdmulpsVps, Wpsmulss (F3)Vss, Wssmulpd (66)Vpd, Wpdmulsd (F2)Vsd, Wsd6punpckhbwPq, Qdpunpckhbw(66)Pdq, QdqpunpckhwdPq, Qdpunpckhwd(66)Pdq, Qdq7VMREADEd/q, Gd/qVMWRITEGd/q, Ed/qP/PENP/POcvtps2pdcvtdq2psVpd, WpsVps, Wdqcvtss2sd (F3) cvtps2dq (66)Vss, WssVdq, Wpscvtpd2ps (66) cvttps2dq (F3)Vps, WpdVdq, Wpscvtsd2ss (F2)Vsd, WsdpunpckhdqPq, Qdpunpckhdq(66)Pdq, QdqpackssdwPq, Qdpackssdw (66)Pdq, QdqL/NGENL/GELE/NGNLE/GsubpsVps, Wpssubss (F3)Vss, Wsssubpd (66)Vpd, Wpdsubsd (F2)Vsd, WsdminpsVps, Wpsminss (F3)Vss, Wssminpd (66)Vpd, Wpdminsd (F2)Vsd, WsddivpsVps, Wpsdivss (F3)Vss, Wssdivpd (66)Vpd, Wpddivsd (F2)Vsd, WsdmaxpsVps, Wpsmaxss (F3)Vss, Wssmaxpd (66)Vpd, Wpdmaxsd (F2)Vsd, Wsdpunpcklqdq(66)Vdq, Wdqpunpckhqdq(66)Vdq, Wdqmovd/q/Pd, Ed/qmovd/q (66)Vdq, Ed/qmovqPq, Qqmovdqa (66)Vdq, Wdqmovdqu (F3)Vdq, Wdqhaddps(F2)Vps, Wpshaddpd(66)Vpd, Wpdhsubps(F2)Vps, Wpshsubpd(66)Vpd, Wpdmovd/qEd/q, Pdmovd/q (66)Ed/q, Vdqmovq (F3)Vq, WqmovqQq, Pqmovdqa (66)Wdq, Vdqmovdqu (F3)Wdq, VdqVol.
2B A-13OPCODE MAPTable A-3. Two-byte Opcode Map: 80H — F7H (First Byte is 0FH) *012ONOB/CNAE9AB34567NE/NZBE/NAA/NBEBE/NAA/NBEJccf64, Jz - Long-displacement jump on condition8AE/NB/NCE/ZSETcc, Eb - Byte Set on conditionONOB/C/NAEAE/NB/NCE/ZNE/NZPUSHd64FSPOPd64FSCPUIDBTEv, GvSHLDEv, Gv, IbSHLDEv, Gv, CLLSSGv, MpBTREv, GvLFSGv, MpLGSGv, MpCMPXCHGEb, GbEv, GvCXADDEb, GbXADDEv, GvcmppsVps, Wps, Ibcmpss (F3)Vss, Wss, Ibcmppd (66)Vpd, Wpd, Ibcmpsd (F2)Vsd, Wsd, IbmovntiMd/q, Gd/qpinsrwPq, Ew, Ibpinsrw (66)Vdq, Ew, IbDaddsubps(F2)Vps, Wpsaddsubpd(66)Vpd, WpdpsrlwPq, Qqpsrlw (66)Vdq, WdqpsrldPq, Qqpsrld (66)Vdq, WdqpsrlqPq, Qqpsrlq (66)Vdq, WdqEpavgbPq, Qqpavgb (66)Vdq, WdqpsrawPq, Qqpsraw (66)Vdq, WdqpsradPq, Qqpsrad (66)Vdq, WdqFlddqu (F2)Vdq, MdqpsllwPq, Qqpsllw (66)Vdq, WdqpslldPq, Qqpslld (66)Vdq, WdqA-14 Vol.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
