Volume 2B Instruction Set Reference N-Z (794102), страница 58
Текст из файла (страница 58)
The source operandcan be an XMM register or a 128-bit memory location. The destination operand is anXMM register.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).OperationDEST[127:0] ← DEST[127:0] BitwiseXOR SRC[127:0];Intel C/C++ Compiler Intrinsic EquivalentXORPS__m128 _mm_xor_ps(__m128 a, __m128 b)SIMD Floating-Point ExceptionsNone.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.XORPS—Bitwise Logical XOR for Single-Precision Floating-Point ValuesVol. 2B 4-423INSTRUCTION SET REFERENCE, N-ZReal-Address Mode Exceptions#GP(0)If a memory operand is not aligned on a 16-byte boundary,regardless of segment.If any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)#GP(0)If a memory address referencing the SS segment is in a noncanonical form.If the memory address is in a non-canonical form.If memory operand is not aligned on a 16-byte boundary,regardless of segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.4-424 Vol.
2BXORPS—Bitwise Logical XOR for Single-Precision Floating-Point ValuesCHAPTER 5VMX INSTRUCTION REFERENCE5.1OVERVIEWThis chapter describes the virtual-machine extensions (VMX) for the Intel 64 andIA-32 architectures. VMX is intended to support virtualization of processor hardwareand a system software layer acting as a host to multiple guest software environments. The virtual-machine extensions (VMX) includes five instructions that managethe virtual-machine control structure (VMCS) and five instruction that manage VMXoperation.
Additional details of VMX are described in IA-32 Intel Architecture Software Developer’s Manual, Volume 3B.The behavior of the VMCS-maintenance instructions is summarized below:•VMPTRLD — This instruction takes a single 64-bit source operand that is inmemory. It makes the referenced VMCS active and current, loading the currentVMCS pointer with this operand and establishes the current VMCS based on thecontents of VMCS-data area in the referenced VMCS region.
Because this makesthe referenced VMCS active, a logical processor may start maintaining on theprocessor some of the VMCS data for the VMCS.•VMPTRST — This instruction takes a single 64-bit destination operand that is inmemory. The current-VMCS pointer is stored into the destination operand.•VMCLEAR — This instruction takes a single 64-bit operand that is in memory.The instruction sets the launch state of the VMCS referenced by the operand to“clear”, renders that VMCS inactive, and ensures that data for the VMCS havebeen written to the VMCS-data area in the referenced VMCS region.
If theoperand is the same as the current-VMCS pointer, that pointer is made invalid.•VMREAD — This instruction reads a component from the VMCS (the encoding ofthat field is given in a register operand) and stores it into a destination operandthat may be a register or in memory.•VMWRITE — This instruction writes a component to the VMCS (the encoding ofthat field is given in a register operand) from a source operand that may be aregister or in memory.The behavior of the VMX management instructions is summarized below:•VMCALL — This instruction allows a guest in VMX non-root operation to call theVMM for service. A VM exit occurs, transferring control to the VMM.•VMLAUNCH — This instruction launches a virtual machine managed by theVMCS.
A VM entry occurs, transferring control to the VM.•VMRESUME — This instruction resumes a virtual machine managed by theVMCS. A VM entry occurs, transferring control to the VM.•VMXOFF — This instruction causes the processor to leave VMX operation.Vol. 2B 5-1VMX INSTRUCTION REFERENCE•VMXON — This instruction takes a single 64-bit source operand that is inmemory. It causes a logical processor to enter VMX root operation and to use thememory referenced by the operand to support VMX operation.Only VMCALL can be executed in compatibility mode (causing a VM exit). The otherVMX instructions generate invalid-opcode exceptions if executed in compatibilitymode.5.2CONVENTIONSThe operation sections for the VMX instructions in Section 5.3 use the pseudo-function VMexit, which indicates that the logical processor performs a VM exit.The operation sections also use the pseudo-functions VMsucceed, VMfail,VMfailInvalid, and VMfailValid.
These pseudo-functions signal instruction success orfailure by setting or clearing bits in RFLAGS and, in some cases, by writing theVM-instruction error field. The following pseudocode fragments detail these functions:VMsucceed:CF ← 0;PF ← 0;AF ← 0;ZF ← 0;SF ← 0;OF ← 0;VMfail(ErrorNumber):IF VMCS pointer is validTHEN VMfailValid(ErrorNumber);ELSE VMfailInvalid;FI;VMfailInvalid:CF ← 1;PF ← 0;AF ← 0;ZF ← 0;SF ← 0;OF ← 0;VMfailValid(ErrorNumber):// executed only if there is a current VMCSCF ← 0;PF ← 0;AF ← 0;ZF ← 1;5-2 Vol.
2BVMX INSTRUCTION REFERENCESF ← 0;OF ← 0;Set the VM-instruction error field to ErrorNumber;The different VM-instruction error numbers are enumerated in Appendix J, “VMInstruction Error Numbers,” in the Intel® 64 and IA-32 Architectures SoftwareDeveloper’s Manual, Volume 3B.5.3VMX INSTRUCTIONSThis section provides detailed descriptions of the VMX instructions.Vol. 2B 5-3VMX INSTRUCTION REFERENCEVMCALL—Call to VM MonitorOpcodeInstructionDescription0F 01 C1VMCALLCall to VM monitor by causing VM exit.DescriptionThis instruction allows guest software can make a call for service into an underlyingVM monitor.
The details of the programming interface for such calls are VMM-specific;this instruction does nothing more than cause a VM exit, registering the appropriateexit reason.Use of this instruction in VMX root operation invokes an SMM monitor (see Section24.16.2 in IA-32 Intel Architecture Software Developer’s Manual, Volume 3B). Thisinvocation will activate the dual-monitor treatment of system-management interrupts(SMIs) and system-management mode (SMM) if it is not already active (see Section24.16.6 in IA-32 Intel Architecture Software Developer’s Manual, Volume 3B).OperationIF not in VMX operationTHEN #UD;ELSIF in VMX non-root operationTHEN VM exit;ELSIF (RFLAGS.VM = 1) OR (IA32_EFER.LMA = 1 and CS.L = 0)THEN #UD;ELSIF CPL > 0THEN #GP(0);ELSIF in SMM or the logical processor does not support the dual-monitor treatment of SMIs andSMM or the valid bit in the IA32_SMM_MONITOR_CTL MSR is clearTHEN VMfail (VMCALL executed in VMX root operation);ELSIF dual-monitor treatment of SMIs and SMM is activeTHEN perform an SMM VM exit (see Section 24.16.2of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B);ELSIF current-VMCS pointer is not validTHEN VMfailInvalid;ELSIF launch state of current VMCS is not clearTHEN VMfailValid(VMCALL with non-clear VMCS);ELSIF VM-exit control fields are not valid (see Section 24.16.6.1 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B)THEN VMfailValid (VMCALL with invalid VM-exit control fields);ELSEenter SMM;read revision identifier in MSEG;5-4 Vol.
2BVMCALL—Call to VM MonitorVMX INSTRUCTION REFERENCEIF revision identifier does not match that supported by processorTHENleave SMM;VMfailValid(VMCALL with incorrect MSEG revision identifier);ELSEread SMM-monitor features field in MSEG (see Section 24.16.6.2,in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B);IF features field is invalidTHENleave SMM;VMfailValid(VMCALL with invalid SMM-monitor features);ELSE activate dual-monitor treatment of SMIs and SMM (see Section 24.16.6in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume3B);FI;FI;FI;Flags AffectedSee the operation section and Section 5.2.Use of PrefixesLOCKCauses #UDREP*Cause #UD (includes REPNE/REPNZ and REP/REPE/REPZ)Segment overrides IgnoredOperand sizeCauses #UDAddress sizeIgnoredREXIgnoredProtected Mode Exceptions#GP(0)If the current privilege level is not 0 and the logical processor isin VMX root operation.#UDIf executed outside VMX operation.Real-Address Mode Exceptions#UDA logical processor cannot be in real-address mode while in VMXoperation and the VMCALL instruction is not recognized outsideVMX operation.VMCALL—Call to VM MonitorVol.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
