Volume 2B Instruction Set Reference N-Z (794102), страница 54
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2BUNPCKHPD—Unpack and Interleave High Packed Double-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, N-Z64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.If memory operand is not aligned on a 16-byte boundary,regardless of segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.UNPCKHPD—Unpack and Interleave High Packed Double-Precision Floating-Point ValuesVol.
2B 4-391INSTRUCTION SET REFERENCE, N-ZUNPCKHPS—Unpack and Interleave High Packed Single-PrecisionFloating-Point ValuesOpcodeInstruction64-BitModeCompat/Leg ModeDescription0F 15 /rUNPCKHPS xmm1,xmm2/m128ValidValidUnpacks and Interleaves singleprecision floating-point valuesfrom high quadwords of xmm1and xmm2/mem into xmm1.DescriptionPerforms an interleaved unpack of the high-order single-precision floating-pointvalues from the source operand (second operand) and the destination operand (firstoperand). See Figure 4-16. The source operand can be an XMM register or a 128-bitmemory location; the destination operand is an XMM register.DESTX3X2SRCY3Y2DESTY3X3X1Y1Y2X0Y0X2Figure 4-16. UNPCKHPS Instruction High Unpack and Interleave OperationWhen unpacking from a memory operand, an implementation may fetch only theappropriate 64 bits; however, alignment to 16-byte boundary and normal segmentchecking will still be enforced.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).OperationDEST[31:0] ← DEST[95:64];DEST[63:32] ← SRC[95:64];DEST[95:64] ← DEST[127:96];DEST[127:96] ← SRC[127:96];4-392 Vol.
2BUNPCKHPS—Unpack and Interleave High Packed Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, N-ZIntel C/C++ Compiler Intrinsic EquivalentUNPCKHPS __m128 _mm_unpackhi_ps(__m128 a, __m128 b)SIMD Floating-Point ExceptionsNone.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.Real-Address Mode Exceptions#GP(0)If a memory operand is not aligned on a 16-byte boundary,regardless of segment.If any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NM#UDIf CR0.TS[bit 3] = 1.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.Compatibility Mode ExceptionsSame exceptions as in protected mode.UNPCKHPS—Unpack and Interleave High Packed Single-Precision Floating-Point ValuesVol.
2B 4-393INSTRUCTION SET REFERENCE, N-Z64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.If memory operand is not aligned on a 16-byte boundary,regardless of segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.4-394 Vol.
2BUNPCKHPS—Unpack and Interleave High Packed Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, N-ZUNPCKLPD—Unpack and Interleave Low Packed Double-PrecisionFloating-Point ValuesOpcodeInstruction64-BitModeCompat/Leg ModeDescription66 0F 14 /rUNPCKLPD xmm1,xmm2/m128ValidValidUnpacks and Interleaves doubleprecision floating-point values fromlow quadwords of xmm1 andxmm2/m128.DescriptionPerforms an interleaved unpack of the low double-precision floating-point valuesfrom the source operand (second operand) and the destination operand (firstoperand). See Figure 4-17. The source operand can be an XMM register or a 128-bitmemory location; the destination operand is an XMM register.DESTX1X0SRCY1Y0DESTY0X0Figure 4-17.
UNPCKLPD Instruction Low Unpack and Interleave OperationWhen unpacking from a memory operand, an implementation may fetch only theappropriate 64 bits; however, alignment to 16-byte boundary and normal segmentchecking will still be enforced.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).OperationDEST[63:0] ← DEST[63:0];DEST[127:64] ← SRC[63:0];UNPCKLPD—Unpack and Interleave Low Packed Double-Precision Floating-Point ValuesVol. 2B 4-395INSTRUCTION SET REFERENCE, N-ZIntel C/C++ Compiler Intrinsic EquivalentUNPCKHPD__m128d _mm_unpacklo_pd(__m128d a, __m128d b)SIMD Floating-Point ExceptionsNone.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.Real-Address Mode Exceptions#GP(0)If a memory operand is not aligned on a 16-byte boundary,regardless of segment.If any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.Compatibility Mode ExceptionsSame exceptions as in protected mode.4-396 Vol.
2BUNPCKLPD—Unpack and Interleave Low Packed Double-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, N-Z64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.If memory operand is not aligned on a 16-byte boundary,regardless of segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.UNPCKLPD—Unpack and Interleave Low Packed Double-Precision Floating-Point ValuesVol.
2B 4-397INSTRUCTION SET REFERENCE, N-ZUNPCKLPS—Unpack and Interleave Low Packed Single-PrecisionFloating-Point ValuesOpcodeInstruction64-BitModeCompat/Leg ModeDescription0F 14 /rUNPCKLPS xmm1,xmm2/m128ValidValidUnpacks and Interleaves singleprecision floating-point values fromlow quadwords of xmm1 andxmm2/mem into xmm1.DescriptionPerforms an interleaved unpack of the low-order single-precision floating-pointvalues from the source operand (second operand) and the destination operand (firstoperand). See Figure 4-18. The source operand can be an XMM register or a 128-bitmemory location; the destination operand is an XMM register.DESTX3X2SRCY3Y2DESTY1X1X1Y1Y0X0Y0X0Figure 4-18.
UNPCKLPS Instruction Low Unpack and Interleave OperationWhen unpacking from a memory operand, an implementation may fetch only theappropriate 64 bits; however, alignment to 16-byte boundary and normal segmentchecking will still be enforced.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).OperationDEST[31:0] ← DEST[31:0];DEST[63:32] ← SRC[31:0];DEST[95:64] ← DEST[63:32];4-398 Vol. 2BUNPCKLPS—Unpack and Interleave Low Packed Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, N-ZDEST[127:96] ← SRC[63:32];Intel C/C++ Compiler Intrinsic EquivalentUNPCKLPS __m128 _mm_unpacklo_ps(__m128 a, __m128 b)SIMD Floating-Point ExceptionsNone.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.Real-Address Mode Exceptions#GP(0)If a memory operand is not aligned on a 16-byte boundary,regardless of segment.If any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NM#UDIf CR0.TS[bit 3] = 1.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.Compatibility Mode ExceptionsSame exceptions as in protected mode.UNPCKLPS—Unpack and Interleave Low Packed Single-Precision Floating-Point ValuesVol.
2B 4-399INSTRUCTION SET REFERENCE, N-Z64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.If memory operand is not aligned on a 16-byte boundary,regardless of segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.4-400 Vol. 2BUNPCKLPS—Unpack and Interleave Low Packed Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, N-ZVERR/VERW—Verify a Segment for Reading or WritingOpcodeInstruction64-BitModeCompat/Leg ModeDescription0F 00 /4VERR r/m16ValidValidSet ZF=1 if segment specified withr/m16 can be read.0F 00 /5VERW r/m16ValidValidSet ZF=1 if segment specified withr/m16 can be written.DescriptionVerifies whether the code or data segment specified with the source operand is readable (VERR) or writable (VERW) from the current privilege level (CPL).
The sourceoperand is a 16-bit register or a memory location that contains the segment selectorfor the segment to be verified. If the segment is accessible and readable (VERR) orwritable (VERW), the ZF flag is set; otherwise, the ZF flag is cleared. Code segmentsare never verified as writable. This check cannot be performed on system segments.To set the ZF flag, the following conditions must be met:••The segment selector is not NULL.•The selector must denote the descriptor of a code or data segment (not that of asystem segment or gate).•••For the VERR instruction, the segment must be readable.The selector must denote a descriptor within the bounds of the descriptor table(GDT or LDT).For the VERW instruction, the segment must be a writable data segment.If the segment is not a conforming code segment, the segment’s DPL must begreater than or equal to (have less or the same privilege as) both the CPL and thesegment selector's RPL.The validation performed is the same as is performed when a segment selector isloaded into the DS, ES, FS, or GS register, and the indicated access (read or write) isperformed.
The segment selector's value cannot result in a protection exception,enabling the software to anticipate possible segment access problems.This instruction’s operation is the same in non-64-bit modes and 64-bit mode. Theoperand size is fixed at 16 bits.OperationIF SRC(Offset) > (GDTR(Limit) or (LDTR(Limit))THEN ZF ← 0; FI;Read segment descriptor;IF SegmentDescriptor(DescriptorType) = 0 (* System segment *)VERR/VERW—Verify a Segment for Reading or WritingVol.
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