Volume 2B Instruction Set Reference N-Z (794102), страница 53
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2BUCOMISD—Unordered Compare Scalar Double-Precision Floating-Point Values and SetEFLAGSINSTRUCTION SET REFERENCE, N-ZIntel C/C++ Compiler Intrinsic Equivalentint _mm_ucomieq_sd(__m128d a, __m128d b)int _mm_ucomilt_sd(__m128d a, __m128d b)int _mm_ucomile_sd(__m128d a, __m128d b)int _mm_ucomigt_sd(__m128d a, __m128d b)int _mm_ucomige_sd(__m128d a, __m128d b)int _mm_ucomineq_sd(__m128d a, __m128d b)SIMD Floating-Point ExceptionsInvalid (if SNaN operands), Denormal.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.Real-Address Mode ExceptionsGP(0)If any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.UCOMISD—Unordered Compare Scalar Double-Precision Floating-Point Values and SetEFLAGSVol.
2B 4-383INSTRUCTION SET REFERENCE, N-ZIf CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.4-384 Vol.
2BUCOMISD—Unordered Compare Scalar Double-Precision Floating-Point Values and SetEFLAGSINSTRUCTION SET REFERENCE, N-ZUCOMISS—Unordered Compare Scalar Single-Precision Floating-PointValues and Set EFLAGSOpcodeInstruction64-BitModeCompat/Leg ModeDescription0F 2E /rUCOMISS xmm1,xmm2/m32ValidValidCompare lower single-precision floatingpoint value in xmm1 register with lowersingle-precision floating-point value inxmm2/mem and set the status flagsaccordingly.DescriptionPerforms and unordered compare of the single-precision floating-point values in thelow doublewords of the source operand 1 (first operand) and the source operand 2(second operand), and sets the ZF, PF, and CF flags in the EFLAGS register accordingto the result (unordered, greater than, less than, or equal).
In The OF, SF and AFflags in the EFLAGS register are set to 0. The unordered result is returned if eithersource operand is a NaN (QNaN or SNaN).Source operand 1 is an XMM register; source operand 2 can be an XMM register or a32 bit memory location.The UCOMISS instruction differs from the COMISS instruction in that it signals aSIMD floating-point invalid operation exception (#I) only when a source operand isan SNaN.
The COMISS instruction signals an invalid operation exception if a sourceoperand is either a QNaN or an SNaN.The EFLAGS register is not updated if an unmasked SIMD floating-point exception isgenerated.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).OperationRESULT ← UnorderedCompare(SRC1[31:0] <> SRC2[31:0]) {(* Set EFLAGS *)CASE (RESULT) OFUNORDERED:ZF,PF,CF ← 111;GREATER_THAN:ZF,PF,CF ← 000;LESS_THAN:ZF,PF,CF ← 001;EQUAL:ZF,PF,CF ← 100;ESAC;OF,AF,SF ← 0;UCOMISS—Unordered Compare Scalar Single-Precision Floating-Point Values and SetEFLAGSVol.
2B 4-385INSTRUCTION SET REFERENCE, N-ZIntel C/C++ Compiler Intrinsic Equivalentint _mm_ucomieq_ss(__m128 a, __m128 b)int _mm_ucomilt_ss(__m128 a, __m128 b)int _mm_ucomile_ss(__m128 a, __m128 b)int _mm_ucomigt_ss(__m128 a, __m128 b)int _mm_ucomige_ss(__m128 a, __m128 b)int _mm_ucomineq_ss(__m128 a, __m128 b)SIMD Floating-Point ExceptionsInvalid (if SNaN operands), Denormal.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.Real-Address Mode ExceptionsGP(0)If any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.4-386 Vol.
2BUCOMISS—Unordered Compare Scalar Single-Precision Floating-Point Values and SetEFLAGSINSTRUCTION SET REFERENCE, N-ZIf CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.UCOMISS—Unordered Compare Scalar Single-Precision Floating-Point Values and SetEFLAGSVol.
2B 4-387INSTRUCTION SET REFERENCE, N-ZUD2—Undefined InstructionOpcodeInstruction64-Bit ModeCompat/Leg ModeDescription0F 0BUD2ValidValidRaise invalid opcode exception.DescriptionGenerates an invalid opcode. This instruction is provided for software testing toexplicitly generate an invalid opcode. The opcode for this instruction is reserved forthis purpose.Other than raising the invalid opcode exception, this instruction is the same as theNOP instruction.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.Operation#UD (* Generates invalid opcode exception *);Flags AffectedNone.Exceptions (All Operating Modes)#UD4-388 Vol. 2BRaises an invalid opcode exception in all operating modes.UD2—Undefined InstructionINSTRUCTION SET REFERENCE, N-ZUNPCKHPD—Unpack and Interleave High Packed Double-PrecisionFloating-Point ValuesOpcodeInstruction64-BitModeCompat/Leg ModeDescription66 0F 15 /rUNPCKHPD xmm1,xmm2/m128ValidValidUnpacks and Interleaves doubleprecision floating-point valuesfrom high quadwords of xmm1and xmm2/m128.DescriptionPerforms an interleaved unpack of the high double-precision floating-point valuesfrom the source operand (second operand) and the destination operand (firstoperand).
See Figure 4-15. The source operand can be an XMM register or a 128-bitmemory location; the destination operand is an XMM register.DESTX1X0SRCY1Y0DESTY1X1Figure 4-15. UNPCKHPD Instruction High Unpack and Interleave OperationWhen unpacking from a memory operand, an implementation may fetch only theappropriate 64 bits; however, alignment to 16-byte boundary and normal segmentchecking will still be enforced.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).OperationDEST[63:0] ← DEST[127:64];DEST[127:64] ← SRC[127:64];UNPCKHPD—Unpack and Interleave High Packed Double-Precision Floating-Point ValuesVol. 2B 4-389INSTRUCTION SET REFERENCE, N-ZIntel C/C++ Compiler Intrinsic EquivalentUNPCKHPD__m128d _mm_unpackhi_pd(__m128d a, __m128d b)SIMD Floating-Point ExceptionsNone.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.Real-Address Mode Exceptions#GP(0)If a memory operand is not aligned on a 16-byte boundary,regardless of segment.If any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.Compatibility Mode ExceptionsSame exceptions as in protected mode.4-390 Vol.
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