Volume 2B Instruction Set Reference N-Z (794102), страница 49
Текст из файла (страница 49)
2B 4-351INSTRUCTION SET REFERENCE, N-Z#SSIf a memory operand effective address is outside the SSsegment limit.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.4-352 Vol.
2BSUB—SubtractINSTRUCTION SET REFERENCE, N-ZSUBPD—Subtract Packed Double-Precision Floating-Point ValuesOpcodeInstruction64-BitModeCompat/Leg ModeDescription66 0F 5C /rSUBPD xmm1,xmm2/m128ValidValidSubtract packed double-precisionfloating-point values inxmm2/m128 from xmm1.DescriptionPerforms a SIMD subtract of the two packed double-precision floating-point values inthe source operand (second operand) from the two packed double-precision floatingpoint values in the destination operand (first operand), and stores the packeddouble-precision floating-point results in the destination operand. The sourceoperand can be an XMM register or a 128-bit memory location.
The destinationoperand is an XMM register. See Figure 11-3 in the Intel® 64 and IA-32 ArchitecturesSoftware Developer’s Manual, Volume 1, for an illustration of a SIMD double-precision floating-point operation.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).OperationDEST[63:0] ← DEST[63:0] − SRC[63:0];DEST[127:64] ← DEST[127:64] − SRC[127:64];Intel C/C++ Compiler Intrinsic EquivalentSUBPD__m128d _mm_sub_pd (m128d a, m128d b)SIMD Floating-Point ExceptionsOverflow, Underflow, Invalid, Precision, Denormal.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.SUBPD—Subtract Packed Double-Precision Floating-Point ValuesVol.
2B 4-353INSTRUCTION SET REFERENCE, N-Z#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 1.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.Real-Address Mode Exceptions#GP(0)If a memory operand is not aligned on a 16-byte boundary,regardless of segment.If any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)#GP(0)If a memory address referencing the SS segment is in a noncanonical form.If the memory address is in a non-canonical form.If memory operand is not aligned on a 16-byte boundary,regardless of segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.4-354 Vol.
2BSUBPD—Subtract Packed Double-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, N-Z#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.SUBPD—Subtract Packed Double-Precision Floating-Point ValuesVol.
2B 4-355INSTRUCTION SET REFERENCE, N-ZSUBPS—Subtract Packed Single-Precision Floating-Point ValuesOpcodeInstruction64-BitModeCompat/Leg ModeDescription0F 5C /rSUBPS xmm1xmm2/m128ValidValidSubtract packed single-precisionfloating-point values in xmm2/memfrom xmm1.DescriptionPerforms a SIMD subtract of the four packed single-precision floating-point values inthe source operand (second operand) from the four packed single-precision floatingpoint values in the destination operand (first operand), and stores the packed singleprecision floating-point results in the destination operand.
The source operand canbe an XMM register or a 128-bit memory location. The destination operand is an XMMregister. See Figure 10-5 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for an illustration of a SIMD double-precision floating-pointoperation.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).OperationDEST[31:0] ← DEST[31:0] − SRC[31:0];DEST[63:32] ← DEST[63:32] − SRC[63:32];DEST[95:64] ← DEST[95:64] − SRC[95:64];DEST[127:96] ← DEST[127:96] − SRC[127:96];Intel C/C++ Compiler Intrinsic EquivalentSUBPS__m128 _mm_sub_ps(__m128 a, __m128 b)SIMD Floating-Point ExceptionsOverflow, Underflow, Invalid, Precision, Denormal.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.4-356 Vol.
2BSUBPS—Subtract Packed Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, N-Z#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.Real-Address Mode Exceptions#GP(0)If a memory operand is not aligned on a 16-byte boundary,regardless of segment.If any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.If memory operand is not aligned on a 16-byte boundary,regardless of segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.SUBPS—Subtract Packed Single-Precision Floating-Point ValuesVol.
2B 4-357INSTRUCTION SET REFERENCE, N-Z#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.4-358 Vol.
2BSUBPS—Subtract Packed Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, N-ZSUBSD—Subtract Scalar Double-Precision Floating-Point ValuesOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionF2 0F 5C /rSUBSD xmm1,xmm2/m64ValidValidSubtracts the low doubleprecision floating-point values inxmm2/mem64 from xmm1.DescriptionSubtracts the low double-precision floating-point value in the source operand(second operand) from the low double-precision floating-point value in the destination operand (first operand), and stores the double-precision floating-point result inthe destination operand.
The source operand can be an XMM register or a 64-bitmemory location. The destination operand is an XMM register. The high quadword ofthe destination operand remains unchanged. See Figure 11-4 in the Intel® 64 andIA-32 Architectures Software Developer’s Manual, Volume 1, for an illustration of ascalar double-precision floating-point operation.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).OperationDEST[63:0] ← DEST[63:0] − SRC[63:0];(* DEST[127:64] unchanged *)Intel C/C++ Compiler Intrinsic EquivalentSUBSD__m128d _mm_sub_sd (m128d a, m128d b)SIMD Floating-Point ExceptionsOverflow, Underflow, Invalid, Precision, Denormal.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.SUBSD—Subtract Scalar Double-Precision Floating-Point ValuesVol.
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