Volume 2B Instruction Set Reference N-Z (794102), страница 45
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If the operand-size attribute is 16 bits, the limitis stored in the low 2 bytes and the 24-bit base address is stored in the third, fourth,and fifth byte, with the sixth byte filled with 0s.In 64-bit mode, the operand size fixed at 8+2 bytes.
The instruction stores 8-bytebase and 2-byte limit values.SIDT is only useful in operating-system software; however, it can be used in application programs without causing an exception to be generated. See “LGDT/LIDT—LoadGlobal/Interrupt Descriptor Table Register” in Chapter 3, Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A, for information on loading theGDTR and IDTR.IA-32 Architecture CompatibilityThe 16-bit form of SIDT is compatible with the Intel 286 processor if the upper 8 bitsare not referenced.
The Intel 286 processor fills these bits with 1s; the Pentium 4,Intel Xeon, P6 processor family, Pentium, Intel486, and Intel386 processors fill thesebits with 0s.OperationIF instruction is SIDTTHENIF OperandSize = 16THENDEST[0:15] ← IDTR(Limit);DEST[16:39] ← IDTR(Base); (* 24 bits of base address stored; *)DEST[40:47] ← 0;ELSE IF (32-bit Operand Size)DEST[0:15] ← IDTR(Limit);DEST[16:47] ← IDTR(Base); FI; (* Full 32-bit base address stored *)ELSE (* 64-bit Operand Size *)DEST[0:15] ← IDTR(Limit);SIDT—Store Interrupt Descriptor Table RegisterVol.
2B 4-317INSTRUCTION SET REFERENCE, N-ZDEST[16:79] ← IDTR(Base); (* Full 64-bit base address stored *)FI;FI;Flags AffectedNone.Protected Mode Exceptions#GP(0)If the destination is located in a non-writable segment.If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register is used to access memory and itcontains a NULL segment selector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.4-318 Vol.
2BSIDT—Store Interrupt Descriptor Table RegisterINSTRUCTION SET REFERENCE, N-Z64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#UDIf the destination operand is a register.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.If the LOCK prefix is used.SIDT—Store Interrupt Descriptor Table RegisterVol. 2B 4-319INSTRUCTION SET REFERENCE, N-ZSLDT—Store Local Descriptor Table RegisterOpcodeInstruction64-BitModeCompat/Leg ModeDescription0F 00 /0SLDT r/m16ValidValidStores segment selector from LDTRin r/m16.REX.W + 0F00 /0SLDT r64/m16ValidValidStores segment selector from LDTRin r64/m16.DescriptionStores the segment selector from the local descriptor table register (LDTR) in thedestination operand.
The destination operand can be a general-purpose register or amemory location. The segment selector stored with this instruction points to thesegment descriptor (located in the GDT) for the current LDT. This instruction can onlybe executed in protected mode.Outside IA-32e mode, when the destination operand is a 32-bit register, the 16-bitsegment selector is copied into the low-order 16 bits of the register. The high-order16 bits of the register are cleared for the Pentium 4, Intel Xeon, and P6 family processors.
They are undefined for Pentium, Intel486, and Intel386 processors. When thedestination operand is a memory location, the segment selector is written to memoryas a 16-bit quantity, regardless of the operand size.In compatibility mode, when the destination operand is a 32-bit register, the 16-bitsegment selector is copied into the low-order 16 bits of the register. The high-order16 bits of the register are cleared.
When the destination operand is a memory location, the segment selector is written to memory as a 16-bit quantity, regardless ofthe operand size.In 64-bit mode, using a REX prefix in the form of REX.R permits access to additionalregisters (R8-R15). The behavior of SLDT with a 64-bit register is to zero-extend the16-bit selector and store it in the register. If the destination is memory and operandsize is 64, SLDT will write the 16-bit selector to memory as a 16-bit quantity, regardless of the operand sizeOperationDEST ← LDTR(SegmentSelector);Flags AffectedNone.Protected Mode Exceptions#GP(0)4-320 Vol. 2BIf the destination is located in a non-writable segment.SLDT—Store Local Descriptor Table RegisterINSTRUCTION SET REFERENCE, N-ZIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register is used to access memory and itcontains a NULL segment selector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#UDThe SLDT instruction is not recognized in real-address mode.If the LOCK prefix is used.Virtual-8086 Mode Exceptions#UDThe SLDT instruction is not recognized in virtual-8086 mode.If the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.SLDT—Store Local Descriptor Table RegisterVol.
2B 4-321INSTRUCTION SET REFERENCE, N-ZSMSW—Store Machine Status WordOpcodeInstruction64-BitModeCompat/Leg ModeDescription0F 01 /4SMSW r/m16ValidValidStore machine status word to r/m16.0F 01 /4SMSW r32/m16ValidValidStore machine status word in low-order16 bits of r32/m16; high-order 16 bitsof r32 are undefined.REX.W + 0F01 /4SMSW r64/m16ValidValidStore machine status word in low-order16 bits of r64/m16; high-order 16 bitsof r32 are undefined.DescriptionStores the machine status word (bits 0 through 15 of control register CR0) into thedestination operand. The destination operand can be a general-purpose register or amemory location.In non-64-bit modes, when the destination operand is a 32-bit register, the low-order16 bits of register CR0 are copied into the low-order 16 bits of the register and thehigh-order 16 bits are undefined.
When the destination operand is a memory location, the low-order 16 bits of register CR0 are written to memory as a 16-bit quantity,regardless of the operand size.In 64-bit mode, the behavior of the SMSW instruction is defined by the followingexamples:••••••SMSW r16 operand size 16, store CR0[15:0] in r16SMSW r32 operand size 32, zero-extend CR0[31:0], and store in r32SMSW r64 operand size 64, zero-extend CR0[63:0], and store in r64SMSW m16 operand size 16, store CR0[15:0] in m16SMSW m16 operand size 32, store CR0[15:0] in m16 (not m32)SMSW m16 operands size 64, store CR0[15:0] in m16 (not m64)SMSW is only useful in operating-system software.
However, it is not a privilegedinstruction and can be used in application programs. The is provided for compatibilitywith the Intel 286 processor. Programs and procedures intended to run on thePentium 4, Intel Xeon, P6 family, Pentium, Intel486, and Intel386 processors shoulduse the MOV (control registers) instruction to load the machine status word.See “Changes to Instruction Behavior in VMX Non-Root Operation” in Chapter 21 ofthe Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B, formore information about the behavior of this instruction in VMX non-root operation.4-322 Vol.
2BSMSW—Store Machine Status WordINSTRUCTION SET REFERENCE, N-ZOperationDEST ← CR0[15:0];(* Machine status word *)Flags AffectedNone.Protected Mode Exceptions#GP(0)If the destination is located in a non-writable segment.If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register is used to access memory and itcontains a NULL segment selector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.SMSW—Store Machine Status WordVol.
2B 4-323INSTRUCTION SET REFERENCE, N-Z64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.4-324 Vol. 2BSMSW—Store Machine Status WordINSTRUCTION SET REFERENCE, N-ZSQRTPD—Compute Square Roots of Packed Double-Precision FloatingPoint ValuesOpcodeInstruction66 0F 51 /r SQRTPD xmm1,xmm2/m12864-BitModeCompat/Leg ModeDescriptionValidValidComputes square roots of thepacked double-precision floatingpoint values in xmm2/m128 andstores the results in xmm1.DescriptionPerforms a SIMD computation of the square roots of the two packed double-precisionfloating-point values in the source operand (second operand) stores the packeddouble-precision floating-point results in the destination operand.
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