Volume 2B Instruction Set Reference N-Z (794102), страница 44
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2BSHRD—Double Precision Shift RightINSTRUCTION SET REFERENCE, N-Zto 6 bits). See the summary chart at the beginning of this section for encoding dataand limits.OperationIF (In 64-Bit Mode and REX.W = 1)THEN COUNT ← COUNT MOD 64;ELSE COUNT ← COUNT MOD 32;FISIZE ← OperandSize;IF COUNT = 0THENNo operation;ELSEIF COUNT > SIZETHEN (* Bad parameters *)DEST is undefined;CF, OF, SF, ZF, AF, PF are undefined;ELSE (* Perform the shift *)CF ← BIT[DEST, COUNT – 1]; (* Last bit shifted out on exit *)FOR i ← 0 TO SIZE – 1 – COUNTDOBIT[DEST, i] ← BIT[DEST, i + COUNT];OD;FOR i ← SIZE – COUNT TO SIZE – 1DOBIT[DEST,i] ← BIT[SRC, i + COUNT – SIZE];OD;FI;FI;Flags AffectedIf the count is 1 or greater, the CF flag is filled with the last bit shifted out of the destination operand and the SF, ZF, and PF flags are set according to the value of theresult. For a 1-bit shift, the OF flag is set if a sign change occurred; otherwise, it iscleared.
For shifts greater than 1 bit, the OF flag is undefined. If a shift occurs, the AFflag is undefined. If the count operand is 0, the flags are not affected. If the count isgreater than the operand size, the flags are undefined.Protected Mode Exceptions#GP(0)If the destination is located in a non-writable segment.If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.SHRD—Double Precision Shift RightVol.
2B 4-309INSTRUCTION SET REFERENCE, N-ZIf the DS, ES, FS, or GS register contains a NULL segmentselector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.4-310 Vol.
2BSHRD—Double Precision Shift RightINSTRUCTION SET REFERENCE, N-ZSHUFPD—Shuffle Packed Double-Precision Floating-Point ValuesOpcodeInstruction66 0F C6 /r ib SHUFPD xmm1,xmm2/m128, imm864-BitModeCompat/Leg ModeDescriptionValidValidShuffle packed double-precisionfloating-point values selected byimm8 from xmm1 andxmm2/m128 to xmm1.DescriptionMoves either of the two packed double-precision floating-point values from destination operand (first operand) into the low quadword of the destination operand;moves either of the two packed double-precision floating-point values from thesource operand into to the high quadword of the destination operand (seeFigure 4-13). The select operand (third operand) determines which values aremoved to the destination operand.DESTX1X0SRCY1Y0DESTY1 or Y0X1 or X0Figure 4-13. SHUFPD Shuffle OperationThe source operand can be an XMM register or a 128-bit memory location.
The destination operand is an XMM register. The select operand is an 8-bit immediate: bit 0selects which value is moved from the destination operand to the result (where 0selects the low quadword and 1 selects the high quadword) and bit 1 selects whichvalue is moved from the source operand to the result. Bits 2 through 7 of the selectoperand are reserved and must be set to 0.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).SHUFPD—Shuffle Packed Double-Precision Floating-Point ValuesVol. 2B 4-311INSTRUCTION SET REFERENCE, N-ZOperationIF SELECT[0] = 0THEN DEST[63:0] ← DEST[63:0];ELSE DEST[63:0] ← DEST[127:64]; FI;IF SELECT[1] = 0THEN DEST[127:64] ← SRC[63:0];ELSE DEST[127:64] ← SRC[127:64]; FI;Intel C/C++ Compiler Intrinsic EquivalentSHUFPD__m128d _mm_shuffle_pd(__m128d a, __m128d b, unsigned int imm8)SIMD Floating-Point ExceptionsNone.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.Real-Address Mode Exceptions#GP(0)If a memory operand is not aligned on a 16-byte boundary,regardless of segment.If any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.4-312 Vol.
2BSHUFPD—Shuffle Packed Double-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, N-ZVirtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If memory operand is not aligned on a 16-byte boundary,regardless of segment.If the memory address is in a non-canonical form.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.SHUFPD—Shuffle Packed Double-Precision Floating-Point ValuesVol. 2B 4-313INSTRUCTION SET REFERENCE, N-ZSHUFPS—Shuffle Packed Single-Precision Floating-Point ValuesOpcodeInstruction64-BitModeCompat/Leg ModeDescription0F C6 /r ibSHUFPS xmm1,xmm2/m128, imm8ValidValidShuffle packed single-precisionfloating-point values selected byimm8 from xmm1 andxmm1/m128 to xmm1.DescriptionMoves two of the four packed single-precision floating-point values from the destination operand (first operand) into the low quadword of the destination operand;moves two of the four packed single-precision floating-point values from the sourceoperand (second operand) into to the high quadword of the destination operand (seeFigure 4-14).
The select operand (third operand) determines which values aremoved to the destination operand.DESTX3SRCY3DESTY3 ... Y0X2Y2X1Y1Y3 ... Y0X3 ... X0X0Y0X3 ... X0Figure 4-14. SHUFPS Shuffle OperationThe source operand can be an XMM register or a 128-bit memory location. The destination operand is an XMM register. The select operand is an 8-bit immediate: bits 0and 1 select the value to be moved from the destination operand to the low doubleword of the result, bits 2 and 3 select the value to be moved from the destinationoperand to the second doubleword of the result, bits 4 and 5 select the value to bemoved from the source operand to the third doubleword of the result, and bits 6 and7 select the value to be moved from the source operand to the high doubleword ofthe result.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).4-314 Vol.
2BSHUFPS—Shuffle Packed Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, N-ZOperationCASE (SELECT[1:0]) OF0: DEST[31:0] ← DEST[31:0];1: DEST[31:0] ← DEST[63:32];2: DEST[31:0] ← DEST[95:64];3: DEST[31:0] ← DEST[127:96];ESAC;CASE (SELECT[3:2]) OF0: DEST[63:32] ← DEST[31:0];1: DEST[63:32] ← DEST[63:32];2: DEST[63:32] ← DEST[95:64];3: DEST[63:32] ← DEST[127:96];ESAC;CASE (SELECT[5:4]) OF0: DEST[95:64] ← SRC[31:0];1: DEST[95:64] ← SRC[63:32];2: DEST[95:64] ← SRC[95:64];3: DEST[95:64] ← SRC[127:96];ESAC;CASE (SELECT[7:6]) OF0: DEST[127:96]1: DEST[127:96]2: DEST[127:96]3: DEST[127:96]ESAC;← SRC[31:0];← SRC[63:32];← SRC[95:64];← SRC[127:96];Intel C/C++ Compiler Intrinsic EquivalentSHUFPS__m128 _mm_shuffle_ps(__m128 a, __m128 b, unsigned int imm8)SIMD Floating-Point ExceptionsNone.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.SHUFPS—Shuffle Packed Single-Precision Floating-Point ValuesVol.
2B 4-315INSTRUCTION SET REFERENCE, N-Z#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.Real-Address Mode Exceptions#GP(0)If a memory operand is not aligned on a 16-byte boundary,regardless of segment.If any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If memory operand is not aligned on a 16-byte boundary,regardless of segment.If the memory address is in a non-canonical form.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.4-316 Vol.
2BSHUFPS—Shuffle Packed Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, N-ZSIDT—Store Interrupt Descriptor Table RegisterOpcodeInstruction64-BitModeCompat/Leg ModeDescription0F 01 /1SIDT mValidValidStore IDTR to m.DescriptionStores the content the interrupt descriptor table register (IDTR) in the destinationoperand. The destination operand specifies a 6-byte memory location.In non-64-bit modes, if the operand-size attribute is 32 bits, the 16-bit limit field ofthe register is stored in the low 2 bytes of the memory location and the 32-bit baseaddress is stored in the high 4 bytes.
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