Volume 2B Instruction Set Reference N-Z (794102), страница 47
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The source operand can be an XMM register or a32-bit memory location. The destination operand is an XMM register. The three highorder doublewords of the destination operand remain unchanged. See Figure 10-6 inthe Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, foran illustration of a scalar single-precision floating-point operation.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).OperationDEST[31:0] ← SQRT (SRC[31:0]);(* DEST[127:64] unchanged *)Intel C/C++ Compiler Intrinsic EquivalentSQRTSS__m128 _mm_sqrt_ss(__m128 a)SIMD Floating-Point ExceptionsInvalid, Precision, Denormal.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.4-334 Vol.
2BSQRTSS—Compute Square Root of Scalar Single-Precision Floating-Point ValueINSTRUCTION SET REFERENCE, N-Z#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.Real-Address Mode ExceptionsGP(0)If any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.SQRTSS—Compute Square Root of Scalar Single-Precision Floating-Point ValueVol.
2B 4-335INSTRUCTION SET REFERENCE, N-Z#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.#AC(0)4-336 Vol. 2BIf alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.SQRTSS—Compute Square Root of Scalar Single-Precision Floating-Point ValueINSTRUCTION SET REFERENCE, N-ZSTC—Set Carry FlagOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionF9STCValidValidSet CF flag.DescriptionSets the CF flag in the EFLAGS register.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.OperationCF ← 1;Flags AffectedThe CF flag is set.
The OF, ZF, SF, AF, and PF flags are unaffected.Exceptions (All Operating Modes)#UDSTC—Set Carry FlagIf the LOCK prefix is used.Vol. 2B 4-337INSTRUCTION SET REFERENCE, N-ZSTD—Set Direction FlagOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionFDSTDValidValidSet DF flag.DescriptionSets the DF flag in the EFLAGS register. When the DF flag is set to 1, string operationsdecrement the index registers (ESI and/or EDI).This instruction’s operation is the same in non-64-bit modes and 64-bit mode.OperationDF ← 1;Flags AffectedThe DF flag is set. The CF, OF, ZF, SF, AF, and PF flags are unaffected.Exceptions (All Operating Modes)#UD4-338 Vol. 2BIf the LOCK prefix is used.STD—Set Direction FlagINSTRUCTION SET REFERENCE, N-ZSTI—Set Interrupt FlagOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionFBSTIValidValidSet interrupt flag; external, maskableinterrupts enabled at the end of thenext instruction.DescriptionIf protected-mode virtual interrupts are not enabled, STI sets the interrupt flag (IF)in the EFLAGS register.
After the IF flag is set, the processor begins responding toexternal, maskable interrupts after the next instruction is executed. The delayedeffect of this instruction is provided to allow interrupts to be enabled just beforereturning from a procedure (or subroutine). For instance, if an STI instruction isfollowed by an RET instruction, the RET instruction is allowed to execute beforeexternal interrupts are recognized1.
If the STI instruction is followed by a CLI instruction (which clears the IF flag), the effect of the STI instruction is negated.The IF flag and the STI and CLI instructions do not prohibit the generation of exceptions and NMI interrupts. NMI interrupts (and SMIs) may be blocked for one macroinstruction following an STI.When protected-mode virtual interrupts are enabled, CPL is 3, and IOPL is less than3; STI sets the VIF flag in the EFLAGS register, leaving IF unaffected.Table 4-4 indicates the action of the STI instruction depending on the processor’smode of operation and the CPL/IOPL settings of the running program or procedure.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.Table 4-4.
Decision Table for STI ResultsPEVMIOPLCPLPVIVIPVMESTI Result0XXXXXXIF = 110≥ CPLXXXXIF = 110< CPL310XVIF = 110< CPL<3XXXGP Fault1. The STI instruction delays recognition of interrupts only if it is executed with EFLAGS.IF = 0. In asequence of STI instructions, only the first instruction in the sequence is guaranteed to delayinterrupts.In the following instruction sequence, interrupts may be recognized before RET executes:STISTIRETSTI—Set Interrupt FlagVol. 2B 4-339INSTRUCTION SET REFERENCE, N-ZTable 4-4. Decision Table for STI ResultsPEVMIOPLCPLPVIVIPVMESTI Result10< CPLX0XXGP Fault10< CPLXX1XGP Fault113XXXXIF = 111<3XX01VIF = 111<3XX1XGP Fault11<3XXX0GP FaultNOTES:X = This setting has no impact.OperationIF PE = 0 (* Executing in real-address mode *)THENIF ← 1; (* Set Interrupt Flag *)ELSE (* Executing in protected mode or virtual-8086 mode *)IF VM = 0 (* Executing in protected mode*)THENIF IOPL ≥ CPLTHENIF ← 1; (* Set Interrupt Flag *)ELSEIF (IOPL < CPL) and (CPL = 3) and (VIP = 0)THENVIF ← 1; (* Set Virtual Interrupt Flag *)ELSE#GP(0);FI;FI;ELSE (* Executing in Virtual-8086 mode *)IF IOPL = 3THENIF ← 1; (* Set Interrupt Flag *)ELSEIF ((IOPL < 3) and (VIP = 0) and (VME = 1))THENVIF ← 1; (* Set Virtual Interrupt Flag *)ELSE#GP(0); (* Trap to virtual-8086 monitor *)FI;)FI;4-340 Vol.
2BSTI—Set Interrupt FlagINSTRUCTION SET REFERENCE, N-ZFI;FI;Flags AffectedThe IF flag is set to 1; or the VIF flag is set to 1.Protected Mode Exceptions#GP(0)If the CPL is greater (has less privilege) than the IOPL of thecurrent program or procedure.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#UDIf the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in protected mode.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode ExceptionsSame exceptions as in protected mode.STI—Set Interrupt FlagVol.
2B 4-341INSTRUCTION SET REFERENCE, N-ZSTMXCSR—Store MXCSR Register StateOpcodeInstruction64-BitModeCompat/Leg ModeDescription0F AE /3STMXCSR m32ValidValidStore contents of MXCSR register tom32.DescriptionStores the contents of the MXCSR control and status register to the destinationoperand. The destination operand is a 32-bit memory location. The reserved bits inthe MXCSR register are stored as 0s.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.Operationm32 ← MXCSR;Intel C/C++ Compiler Intrinsic Equivalent_mm_getcsr(void)ExceptionsNone.Numeric ExceptionsNone.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS, or GS segments.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#UDIf CR0.EM[bit 2] = 1.#NMIf CR0.TS[bit 3] = 1.#ACFor unaligned memory reference.
To enable #AC exceptions,three conditions must be true: CR0.AM[bit 18] = 1,EFLAGS.AC[bit 18] = 1, current CPL = 3.#UDIf CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.4-342 Vol. 2BSTMXCSR—Store MXCSR Register StateINSTRUCTION SET REFERENCE, N-ZReal Address Mode ExceptionsGP(0)If any part of the operand would lie outside of the effectiveaddress space from 0 to 0FFFFH.#UDIf CR0.EM[bit 2] = 1.#NMIf CR0.TS[bit 3] = 1.#UDIf CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.Virtual 8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.#ACFor unaligned memory reference.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#ACFor unaligned memory reference.
To enable #AC exceptions,three conditions must be true: CR0.AM[bit 18] = 1,EFLAGS.AC[bit 18] = 1, current CPL = 3#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.STMXCSR—Store MXCSR Register StateVol. 2B 4-343INSTRUCTION SET REFERENCE, N-ZSTOS/STOSB/STOSW/STOSD/STOSQ—Store StringOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionAASTOS m8ValidValidFor legacy mode, store AL at addressES:(E)DI; For 64-bit mode store AL ataddress RDI or EDI.ABSTOS m16ValidValidFor legacy mode, store AX at addressES:(E)DI; For 64-bit mode store AX ataddress RDI or EDI.ABSTOS m32ValidValidFor legacy mode, store EAX at addressES:(E)DI; For 64-bit mode store EAX ataddress RDI or EDI.REX.W + ABSTOS m64ValidN.E.Store RAX at address RDI or EDI.AASTOSBValidValidFor legacy mode, store AL at addressES:(E)DI; For 64-bit mode store AL ataddress RDI or EDI.ABSTOSWValidValidFor legacy mode, store AX at addressES:(E)DI; For 64-bit mode store AX ataddress RDI or EDI.ABSTOSDValidValidFor legacy mode, store EAX at addressES:(E)DI; For 64-bit mode store EAX ataddress RDI or EDI.REX.W + ABSTOSQValidN.E.Store RAX at address RDI or EDI.DescriptionIn non-64-bit and default 64-bit mode; stores a byte, word, or doubleword from theAL, AX, or EAX register (respectively) into the destination operand.
The destinationoperand is a memory location, the address of which is read from either the ES:EDI orES:DI register (depending on the address-size attribute of the instruction and themode of operation). The ES segment cannot be overridden with a segment overrideprefix.At the assembly-code level, two forms of the instruction are allowed: the “explicitoperands” form and the “no-operands” form. The explicit-operands form (specifiedwith the STOS mnemonic) allows the destination operand to be specified explicitly.Here, the destination operand should be a symbol that indicates the size and locationof the destination value.
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