Volume 2B Instruction Set Reference N-Z (794102), страница 42
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2BSCAS/SCASB/SCASW/SCASD—Scan StringINSTRUCTION SET REFERENCE, N-Z#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.SCAS/SCASB/SCASW/SCASD—Scan StringVol. 2B 4-295INSTRUCTION SET REFERENCE, N-ZSETcc—Set Byte on ConditionOpcodeInstruction64-BitModeCompat/Leg ModeDescription0F 97SETA r/m8ValidValidSet byte if above (CF=0 andZF=0).REX + 0F 97SETA r/m8*ValidN.E.Set byte if above (CF=0 andZF=0).0F 93SETAE r/m8ValidValidSet byte if above or equal (CF=0).REX + 0F 93SETAE r/m8*ValidN.E.Set byte if above or equal (CF=0).0F 92SETB r/m8ValidValidSet byte if below (CF=1).REX + 0F 92SETB r/m8*ValidN.E.Set byte if below (CF=1).0F 96SETBE r/m8ValidValidSet byte if below or equal (CF=1or ZF=1).REX + 0F 96SETBE r/m8*ValidN.E.Set byte if below or equal (CF=1or ZF=1).0F 92SETC r/m8ValidValidSet byte if carry (CF=1).REX + 0F 92SETC r/m8*ValidN.E.Set byte if carry (CF=1).0F 94SETE r/m8ValidValidSet byte if equal (ZF=1).REX + 0F 94SETE r/m8*ValidN.E.Set byte if equal (ZF=1).0F 9FSETG r/m8ValidValidSet byte if greater (ZF=0 andSF=OF).REX + 0F 9FSETG r/m8*ValidN.E.Set byte if greater (ZF=0 andSF=OF).0F 9DSETGE r/m8ValidValidSet byte if greater or equal(SF=OF).REX + 0F 9DSETGE r/m8*ValidN.E.Set byte if greater or equal(SF=OF).0F 9CSETL r/m8ValidValidSet byte if less (SF≠ OF).REX + 0F 9CSETL r/m8*ValidN.E.Set byte if less (SF≠ OF).0F 9ESETLE r/m8ValidValidSet byte if less or equal (ZF=1 orSF≠ OF).REX + 0F 9ESETLE r/m8*ValidN.E.Set byte if less or equal (ZF=1 orSF≠ OF).0F 96SETNA r/m8ValidValidSet byte if not above (CF=1 orZF=1).REX + 0F 96SETNA r/m8*ValidN.E.Set byte if not above (CF=1 orZF=1).4-296 Vol.
2BSETcc—Set Byte on ConditionINSTRUCTION SET REFERENCE, N-ZOpcodeInstruction64-BitModeCompat/Leg ModeDescription0F 92SETNAE r/m8ValidValidSet byte if not above or equal(CF=1).REX + 0F 92SETNAE r/m8*ValidN.E.Set byte if not above or equal(CF=1).0F 93SETNB r/m8ValidValidSet byte if not below (CF=0).REX + 0F 93SETNB r/m8*ValidN.E.Set byte if not below (CF=0).0F 97SETNBE r/m8ValidValidSet byte if not below or equal(CF=0 and ZF=0).REX + 0F 97SETNBE r/m8*ValidN.E.Set byte if not below or equal(CF=0 and ZF=0).0F 93SETNC r/m8ValidValidSet byte if not carry (CF=0).REX + 0F 93SETNC r/m8*ValidN.E.Set byte if not carry (CF=0).0F 95SETNE r/m8ValidValidSet byte if not equal (ZF=0).REX + 0F 95SETNE r/m8*ValidN.E.Set byte if not equal (ZF=0).0F 9ESETNG r/m8ValidValidSet byte if not greater (ZF=1 orSF≠ OF)REX + 0F 9ESETNG r/m8*ValidN.E.Set byte if not greater (ZF=1 orSF≠ OF).0F 9CSETNGE r/m8ValidValidSet byte if not greater or equal(SF≠ OF).REX + 0F 9CSETNGE r/m8*ValidN.E.Set byte if not greater or equal(SF≠ OF).0F 9DSETNL r/m8ValidValidSet byte if not less (SF=OF).REX + 0F 9DSETNL r/m8*ValidN.E.Set byte if not less (SF=OF).0F 9FSETNLE r/m8ValidValidSet byte if not less or equal (ZF=0and SF=OF).REX + 0F 9FSETNLE r/m8*ValidN.E.Set byte if not less or equal (ZF=0and SF=OF).0F 91SETNO r/m8ValidValidSet byte if not overflow (OF=0).REX + 0F 91SETNO r/m8*ValidN.E.Set byte if not overflow (OF=0).0F 9BSETNP r/m8ValidValidSet byte if not parity (PF=0).REX + 0F 9BSETNP r/m8*ValidN.E.Set byte if not parity (PF=0).0F 99SETNS r/m8ValidValidSet byte if not sign (SF=0).REX + 0F 99SETNS r/m8*ValidN.E.Set byte if not sign (SF=0).0F 95SETNZ r/m8ValidValidSet byte if not zero (ZF=0).SETcc—Set Byte on ConditionVol.
2B 4-297INSTRUCTION SET REFERENCE, N-ZOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionREX + 0F 95SETNZ r/m8*ValidN.E.Set byte if not zero (ZF=0).0F 90SETO r/m8ValidValidSet byte if overflow (OF=1)REX + 0F 90SETO r/m8*ValidN.E.Set byte if overflow (OF=1).0F 9ASETP r/m8ValidValidSet byte if parity (PF=1).REX + 0F 9ASETP r/m8*ValidN.E.Set byte if parity (PF=1).0F 9ASETPE r/m8ValidValidSet byte if parity even (PF=1).REX + 0F 9ASETPE r/m8*ValidN.E.Set byte if parity even (PF=1).0F 9BSETPO r/m8ValidValidSet byte if parity odd (PF=0).REX + 0F 9BSETPO r/m8*ValidN.E.Set byte if parity odd (PF=0).0F 98SETS r/m8ValidValidSet byte if sign (SF=1).REX + 0F 98SETS r/m8*ValidN.E.Set byte if sign (SF=1).0F 94SETZ r/m8ValidValidSet byte if zero (ZF=1).REX + 0F 94SETZ r/m8*ValidN.E.Set byte if zero (ZF=1).NOTES:* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix isused: AH, BH, CH, DH.DescriptionSets the destination operand to 0 or 1 depending on the settings of the status flags(CF, SF, OF, ZF, and PF) in the EFLAGS register.
The destination operand points to abyte register or a byte in memory. The condition code suffix (cc) indicates the condition being tested for.The terms “above” and “below” are associated with the CF flag and refer to the relationship between two unsigned integer values. The terms “greater” and “less” areassociated with the SF and OF flags and refer to the relationship between two signedinteger values.Many of the SETcc instruction opcodes have alternate mnemonics.
For example,SETG (set byte if greater) and SETNLE (set if not less or equal) have the sameopcode and test for the same condition: ZF equals 0 and SF equals OF. These alternate mnemonics are provided to make code more intelligible. Appendix B, “EFLAGSCondition Codes,” in the Intel® 64 and IA-32 Architectures Software Developer’sManual, Volume 1, shows the alternate mnemonics for various test conditions.Some languages represent a logical one as an integer with all bits set. This representation can be obtained by choosing the logically opposite condition for the SETccinstruction, then decrementing the result.
For example, to test for overflow, use theSETNO instruction, then decrement the result.4-298 Vol. 2BSETcc—Set Byte on ConditionINSTRUCTION SET REFERENCE, N-ZIn IA-64 mode, the operand size is fixed at 8 bits. Use of REX prefix enable uniformaddressing to additional byte registers. Otherwise, this instruction’s operation is thesame as in legacy mode and compatibility mode.OperationIF conditionTHEN DEST ← 1;ELSE DEST ← 0;FI;Flags AffectedNone.Protected Mode Exceptions#GP(0)If the destination is located in a non-writable segment.If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a NULL segmentselector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#UDIf the LOCK prefix is used.SETcc—Set Byte on ConditionVol.
2B 4-299INSTRUCTION SET REFERENCE, N-ZCompatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)If a page fault occurs.#UDIf the LOCK prefix is used.4-300 Vol. 2BSETcc—Set Byte on ConditionINSTRUCTION SET REFERENCE, N-ZSFENCE—Store FenceOpcodeInstruction64-BitModeCompat/Leg ModeDescription0F AE /7SFENCEValidValidSerializes store operations.DescriptionPerforms a serializing operation on all store-to-memory instructions that were issuedprior the SFENCE instruction. This serializing operation guarantees that every storeinstruction that precedes in program order the SFENCE instruction is globally visiblebefore any store instruction that follows the SFENCE instruction is globally visible.The SFENCE instruction is ordered with respect store instructions, other SFENCEinstructions, any MFENCE instructions, and any serializing instructions (such as theCPUID instruction).
It is not ordered with respect to load instructions or the LFENCEinstruction.Weakly ordered memory types can be used to achieve higher processor performancethrough such techniques as out-of-order issue, write-combining, and writecollapsing. The degree to which a consumer of data recognizes or knows that thedata is weakly ordered varies among applications and may be unknown to theproducer of this data. The SFENCE instruction provides a performance-efficient wayof insuring store ordering between routines that produce weakly-ordered results androutines that consume this data.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.OperationWait_On_Following_Stores_Until(preceding_stores_globally_visible);Intel C/C++ Compiler Intrinsic Equivalentvoid _mm_sfence(void)Exceptions (All Operating Modes)#UDSFENCE—Store FenceIf the LOCK prefix is used.Vol.
2B 4-301INSTRUCTION SET REFERENCE, N-ZSGDT—Store Global Descriptor Table RegisterOpcode*Instruction64-BitModeCompat/Leg ModeDescription0F 01 /0SGDT mValidValidStore GDTR to m.NOTES:* See IA-32 Architecture Compatibility section below.DescriptionStores the content of the global descriptor table register (GDTR) in the destinationoperand. The destination operand specifies a memory location.In legacy or compatibility mode, the destination operand is a 6-byte memory location. If the operand-size attribute is 16 bits, the limit is stored in the low 2 bytes andthe 24-bit base address is stored in bytes 3-5, and byte 6 is zero-filled. If theoperand-size attribute is 32 bits, the 16-bit limit field of the register is stored in thelow 2 bytes of the memory location and the 32-bit base address is stored in the high4 bytes.In IA-32e mode, the operand size is fixed at 8+2 bytes.
The instruction stores an 8byte base and a 2-byte limit.SGDT is useful only by operating-system software. However, it can be used in application programs without causing an exception to be generated. See“LGDT/LIDT—Load Global/Interrupt Descriptor Table Register” in Chapter 3, Intel®64 and IA-32 Architectures Software Developer’s Manual, Volume 2A, for informationon loading the GDTR and IDTR.IA-32 Architecture CompatibilityThe 16-bit form of the SGDT is compatible with the Intel 286 processor if the upper 8bits are not referenced.
The Intel 286 processor fills these bits with 1s; the Pentium4, Intel Xeon, P6 processor family, Pentium, Intel486, and Intel386™ processors fillthese bits with 0s.OperationIF instruction is SGDTIF OperandSize = 16THENDEST[0:15] ← GDTR(Limit);DEST[16:39] ← GDTR(Base); (* 24 bits of base address stored *)DEST[40:47] ← 0;ELSE IF (32-bit Operand Size)DEST[0:15] ← GDTR(Limit);DEST[16:47] ← GDTR(Base); (* Full 32-bit base address stored *)4-302 Vol.
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