Volume 2B Instruction Set Reference N-Z (794102), страница 43
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2BSGDT—Store Global Descriptor Table RegisterINSTRUCTION SET REFERENCE, N-ZFI;ELSE (* 64-bit Operand Size *)DEST[0:15] ← GDTR(Limit);DEST[16:79] ← GDTR(Base); (* Full 64-bit base address stored *)FI;FI;Flags AffectedNone.Protected Mode Exceptions#UDIf the destination operand is a register.If the LOCK prefix is used.#GP(0)If the destination is located in a non-writable segment.If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register is used to access memory and itcontains a NULL segment selector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.Real-Address Mode Exceptions#UDIf the destination operand is a register.If the LOCK prefix is used.#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.Virtual-8086 Mode Exceptions#UDIf the destination operand is a register.If the LOCK prefix is used.#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.SGDT—Store Global Descriptor Table RegisterVol.
2B 4-303INSTRUCTION SET REFERENCE, N-Z#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#UDIf the destination operand is a register.If the LOCK prefix is used.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.4-304 Vol. 2BSGDT—Store Global Descriptor Table RegisterINSTRUCTION SET REFERENCE, N-ZSHLD—Double Precision Shift LeftOpcodeInstruction64-BitModeCompat/Leg ModeDescription0F A4SHLD r/m16, r16,imm8ValidValidShift r/m16 to left imm8places while shifting bitsfrom r16 in from the right.0F A5SHLD r/m16, r16, CL ValidValidShift r/m16 to left CL placeswhile shifting bits from r16in from the right.0F A4SHLD r/m32, r32,imm8ValidValidShift r/m32 to left imm8places while shifting bitsfrom r32 in from the right.REX.W + 0F A4SHLD r/m64, r64,imm8ValidN.E.Shift r/m64 to left imm8places while shifting bitsfrom r64 in from the right.0F A5SHLD r/m32, r32, CL ValidValidShift r/m32 to left CL placeswhile shifting bits from r32in from the right.REX.W + 0F A5SHLD r/m64, r64, CL ValidN.E.Shift r/m64 to left CL placeswhile shifting bits from r64in from the right.DescriptionThe SHLD instruction is used for multi-precision shifts of 64 bits or more.The instruction shifts the first operand (destination operand) to the left the numberof bits specified by the third operand (count operand).
The second operand (sourceoperand) provides bits to shift in from the right (starting with bit 0 of the destinationoperand).The destination operand can be a register or a memory location; the source operandis a register. The count operand is an unsigned integer that can be stored in an immediate byte or in the CL register. If the count operand is CL, the shift count is thelogical AND of CL and a count mask. In non-64-bit modes and default 64-bit mode;only bits 0 through 4 of the count are used. This masks the count to a value between0 and 31.
If a count is greater than the operand size, the result is undefined.If the count is 1 or greater, the CF flag is filled with the last bit shifted out of the destination operand. For a 1-bit shift, the OF flag is set if a sign change occurred; otherwise, it is cleared. If the count operand is 0, flags are not affected.In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefixin the form of REX.R permits access to additional registers (R8-R15). Using a REXprefix in the form of REX.W promotes operation to 64 bits (upgrading the count maskSHLD—Double Precision Shift LeftVol.
2B 4-305INSTRUCTION SET REFERENCE, N-Zto 6 bits). See the summary chart at the beginning of this section for encoding dataand limits.OperationIF (In 64-Bit Mode and REX.W = 1)THEN COUNT ← COUNT MOD 64;ELSE COUNT ← COUNT MOD 32;FISIZE ← OperandSize;IF COUNT = 0THENNo operation;ELSEIF COUNT > SIZETHEN (* Bad parameters *)DEST is undefined;CF, OF, SF, ZF, AF, PF are undefined;ELSE (* Perform the shift *)CF ← BIT[DEST, SIZE – COUNT];(* Last bit shifted out on exit *)FOR i ← SIZE – 1 DOWN TO COUNTDOBit(DEST, i) ← Bit(DEST, i – COUNT);OD;FOR i ← COUNT – 1 DOWN TO 0DOBIT[DEST, i] ← BIT[SRC, i – COUNT + SIZE];OD;FI;FI;Flags AffectedIf the count is 1 or greater, the CF flag is filled with the last bit shifted out of the destination operand and the SF, ZF, and PF flags are set according to the value of theresult. For a 1-bit shift, the OF flag is set if a sign change occurred; otherwise, it iscleared.
For shifts greater than 1 bit, the OF flag is undefined. If a shift occurs, the AFflag is undefined. If the count operand is 0, the flags are not affected. If the count isgreater than the operand size, the flags are undefined.Protected Mode Exceptions#GP(0)4-306 Vol. 2BIf the destination is located in a non-writable segment.SHLD—Double Precision Shift LeftINSTRUCTION SET REFERENCE, N-ZIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a NULL segmentselector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.SHLD—Double Precision Shift LeftVol.
2B 4-307INSTRUCTION SET REFERENCE, N-ZSHRD—Double Precision Shift RightOpcodeInstruction64-BitModeCompat/Leg ModeDescription0F ACSHRD r/m16,r16, imm8ValidValidShift r/m16 to right imm8 placeswhile shifting bits from r16 infrom the left.0F ADSHRD r/m16,r16, CLValidValidShift r/m16 to right CL placeswhile shifting bits from r16 infrom the left.0F ACSHRD r/m32,r32, imm8ValidValidShift r/m32 to right imm8 placeswhile shifting bits from r32 infrom the left.REX.W + 0F ACSHRD r/m64,r64, imm8ValidN.E.Shift r/m64 to right imm8 placeswhile shifting bits from r64 infrom the left.0F ADSHRD r/m32,r32, CLValidValidShift r/m32 to right CL placeswhile shifting bits from r32 infrom the left.REX.W + 0F ADSHRD r/m64,r64, CLValidN.E.Shift r/m64 to right CL placeswhile shifting bits from r64 infrom the left.DescriptionThe SHRD instruction is useful for multi-precision shifts of 64 bits or more.The instruction shifts the first operand (destination operand) to the right the numberof bits specified by the third operand (count operand).
The second operand (sourceoperand) provides bits to shift in from the left (starting with the most significant bitof the destination operand).The destination operand can be a register or a memory location; the source operandis a register. The count operand is an unsigned integer that can be stored in an immediate byte or the CL register. If the count operand is CL, the shift count is the logicalAND of CL and a count mask. In non-64-bit modes and default 64-bit mode, thewidth of the count mask is 5 bits. Only bits 0 through 4 of the count register are used(masking the count to a value between 0 and 31).
If the count is greater than theoperand size, the result is undefined.If the count is 1 or greater, the CF flag is filled with the last bit shifted out of the destination operand. For a 1-bit shift, the OF flag is set if a sign change occurred; otherwise, it is cleared. If the count operand is 0, flags are not affected.In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefixin the form of REX.R permits access to additional registers (R8-R15). Using a REXprefix in the form of REX.W promotes operation to 64 bits (upgrading the count mask4-308 Vol.
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