Volume 2B Instruction Set Reference N-Z (794102), страница 46
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The sourceoperand can be an XMM register or a 128-bit memory location. The destinationoperand is an XMM register. See Figure 11-3 in the Intel® 64 and IA-32 ArchitecturesSoftware Developer’s Manual, Volume 1, for an illustration of a SIMD double-precision floating-point operation.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).OperationDEST[63:0] ← SQRT(SRC[63:0]);DEST[127:64] ← SQRT(SRC[127:64]);Intel C/C++ Compiler Intrinsic EquivalentSQRTPD__m128d _mm_sqrt_pd (m128d a)SIMD Floating-Point ExceptionsInvalid, Precision, Denormal.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.SMSW—Store Machine Status WordVol.
2B 4-325INSTRUCTION SET REFERENCE, N-Z#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.CR4.OSXMMEXCPT(bit 10) is 1.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.Real-Address Mode Exceptions#GP(0)If a memory operand is not aligned on a 16-byte boundary,regardless of segment.If any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)#GP(0)If a memory address referencing the SS segment is in a noncanonical form.If the memory address is in a non-canonical form.If memory operand is not aligned on a 16-byte boundary,regardless of segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.4-326 Vol.
2BSMSW—Store Machine Status WordINSTRUCTION SET REFERENCE, N-Z#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.SMSW—Store Machine Status WordVol. 2B 4-327INSTRUCTION SET REFERENCE, N-ZSQRTPS—Compute Square Roots of Packed Single-Precision FloatingPoint ValuesOpcodeInstruction64-BitModeCompat/Leg ModeDescription0F 51 /rSQRTPS xmm1,xmm2/m128ValidValidComputes square roots of the packedsingle-precision floating-point values inxmm2/m128 and stores the results inxmm1.DescriptionPerforms a SIMD computation of the square roots of the four packed single-precisionfloating-point values in the source operand (second operand) stores the packedsingle-precision floating-point results in the destination operand.
The source operandcan be an XMM register or a 128-bit memory location. The destination operand is anXMM register. See Figure 10-5 in the Intel® 64 and IA-32 Architectures SoftwareDeveloper’s Manual, Volume 1, for an illustration of a SIMD single-precision floatingpoint operation.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).OperationDEST[31:0] ← SQRT(SRC[31:0]);DEST[63:32] ← SQRT(SRC[63:32]);DEST[95:64] ← SQRT(SRC[95:64]);DEST[127:96] ← SQRT(SRC[127:96]);Intel C/C++ Compiler Intrinsic EquivalentSQRTPS__m128 _mm_sqrt_ps(__m128 a)SIMD Floating-Point ExceptionsInvalid, Precision, Denormal.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.4-328 Vol.
2BSQRTPS—Compute Square Roots of Packed Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, N-Z#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.Real-Address Mode Exceptions#GP(0)If a memory operand is not aligned on a 16-byte boundary,regardless of segment.If any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.If memory operand is not aligned on a 16-byte boundary,regardless of segment.#PF(fault-code)For a page fault.SQRTPS—Compute Square Roots of Packed Single-Precision Floating-Point ValuesVol.
2B 4-329INSTRUCTION SET REFERENCE, N-Z#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.4-330 Vol. 2BSQRTPS—Compute Square Roots of Packed Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, N-ZSQRTSD—Compute Square Root of Scalar Double-Precision FloatingPoint ValueOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionF2 0F 51 /rSQRTSD xmm1,xmm2/m64ValidValidComputes square root of thelow double-precision floatingpoint value in xmm2/m64 andstores the results in xmm1.DescriptionComputes the square root of the low double-precision floating-point value in thesource operand (second operand) and stores the double-precision floating-pointresult in the destination operand.
The source operand can be an XMM register or a64-bit memory location. The destination operand is an XMM register. The high quadword of the destination operand remains unchanged. See Figure 11-4 in the Intel®64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for an illustration of a scalar double-precision floating-point operation.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).OperationDEST[63:0] ← SQRT(SRC[63:0]);(* DEST[127:64] unchanged *)Intel C/C++ Compiler Intrinsic EquivalentSQRTSD__m128d _mm_sqrt_sd (m128d a)SIMD Floating-Point ExceptionsInvalid, Precision, Denormal.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.SQRTSD—Compute Square Root of Scalar Double-Precision Floating-Point ValueVol.
2B 4-331INSTRUCTION SET REFERENCE, N-Z#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.Real-Address Mode ExceptionsGP(0)If any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.4-332 Vol.
2BSQRTSD—Compute Square Root of Scalar Double-Precision Floating-Point ValueINSTRUCTION SET REFERENCE, N-Z#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.SQRTSD—Compute Square Root of Scalar Double-Precision Floating-Point ValueVol. 2B 4-333INSTRUCTION SET REFERENCE, N-ZSQRTSS—Compute Square Root of Scalar Single-Precision FloatingPoint ValueOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionF3 0F 51 /rSQRTSS xmm1,xmm2/m32ValidValidComputes square root of the lowsingle-precision floating-point valuein xmm2/m32 and stores theresults in xmm1.DescriptionComputes the square root of the low single-precision floating-point value in thesource operand (second operand) and stores the single-precision floating-pointresult in the destination operand.
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