Volume 2B Instruction Set Reference N-Z (794102), страница 50
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2B 4-359INSTRUCTION SET REFERENCE, N-ZIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.Real-Address Mode ExceptionsGP(0)If any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.4-360 Vol.
2BSUBSD—Subtract Scalar Double-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, N-Z#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.SUBSD—Subtract Scalar Double-Precision Floating-Point ValuesVol. 2B 4-361INSTRUCTION SET REFERENCE, N-ZSUBSS—Subtract Scalar Single-Precision Floating-Point ValuesOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionF3 0F 5C /rSUBSS xmm1,xmm2/m32ValidValidSubtract the lower single-precisionfloating-point values in xmm2/m32from xmm1.DescriptionSubtracts the low single-precision floating-point value in the source operand (secondoperand) from the low single-precision floating-point value in the destinationoperand (first operand), and stores the single-precision floating-point result in thedestination operand.
The source operand can be an XMM register or a 32-bit memorylocation. The destination operand is an XMM register. The three high-order doublewords of the destination operand remain unchanged. See Figure 10-6 in the Intel®64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for an illustration of a scalar single-precision floating-point operation.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).OperationDEST[31:0] ← DEST[31:0] − SRC[31:0];(* DEST[127:96] unchanged *)Intel C/C++ Compiler Intrinsic EquivalentSUBSS__m128 _mm_sub_ss(__m128 a, __m128 b)SIMD Floating-Point ExceptionsOverflow, Underflow, Invalid, Precision, Denormal.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.4-362 Vol.
2BSUBSS—Subtract Scalar Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, N-Z#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.Real-Address Mode ExceptionsGP(0)If any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.SUBSS—Subtract Scalar Single-Precision Floating-Point ValuesVol.
2B 4-363INSTRUCTION SET REFERENCE, N-Z#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.#AC(0)4-364 Vol. 2BIf alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.SUBSS—Subtract Scalar Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, N-ZSWAPGS—Swap GS Base RegisterOpcodeInstruction64-BitModeCompat/Leg ModeDescription0F 01 /7SWAPGSValidInvalidExchanges the current GS base registervalue with the value contained in MSRaddress C0000102H.DescriptionSWAPGS exchanges the current GS base register value with the value contained inMSR address C0000102H (MSR_KERNELGSbase).
KernelGSbase is guaranteed to becanonical; so SWAPGS does not perform a canonical check. The SWAPGS instructionis a privileged instruction intended for use by system software.When using SYSCALL to implement system calls, there is no kernel stack at the OSentry point. Neither is there a straightforward method to obtain a pointer to kernelstructures from which the kernel stack pointer could be read. Thus, the kernel can'tsave general purpose registers or reference memory.By design, SWAPGS does not require any general purpose registers or memory operands.
No registers need to be saved before using the instruction. SWAPGS exchangesthe CPL 0 data pointer from the KernelGSbase MSR with the GS base register. Thekernel can then use the GS prefix on normal memory references to access kerneldata structures. Similarly, when the OS kernel is entered using an interrupt or exception (where the kernel stack is already set up), SWAPGS can be used to quickly get apointer to the kernel data structures.The KernelGSbase MSR itself is only accessible using RDMSR/WRMSR instructions.Those instructions are only accessible at privilege level 0. WRMSR will cause a#GP(0) if the value to be written to KernelGSbase MSR is non-canonical.See Table 4-5.Table 4-5. SWAPGS Operation ParametersOpcodeOF 01ModR/M ByteInstructionMODREGR/MNot 64-bitMode64-bit ModeMOD ≠ 11111xxxINVLPGINVLPG11111000#UDSWPGS11111≠ 000#UD#UDSWAPGS—Swap GS Base RegisterVol.
2B 4-365INSTRUCTION SET REFERENCE, N-ZOperationIF CS.L ≠ 1 (* Not in 64-Bit Mode *)THEN#UD; FI;IF CPL ≠ 0THEN #GP(0); FI;tmp ← GS(BASE);GS(BASE) ← KERNELGSbase;KERNELGSbase ← tmp;Flags AffectedNoneProtected Mode Exceptions#UDIf Mode≠ 64-Bit.Real-Address Mode Exceptions#UDIf Mode≠ 64-Bit.Virtual-8086 Mode Exceptions#UDIf Mode≠ 64-Bit.Compatibility Mode Exceptions#UDIf Mode≠ 64-Bit.64-Bit Mode Exceptions#GP(0)If CPL≠ 0.If the LOCK prefix is used.4-366 Vol. 2BSWAPGS—Swap GS Base RegisterINSTRUCTION SET REFERENCE, N-ZSYSCALL—Fast System CallOpcodeInstruction64-BitModeCompat/Leg ModeDescription0F 05SYSCALLValidInvalidFast call to privilege level 0system procedures.DescriptionSYSCALL saves the RIP of the instruction following SYSCALL to RCX and loads a newRIP from the IA32_LSTAR (64-bit mode).
Upon return, SYSRET copies the valuesaved in RCX to the RIP.SYSCALL saves RFLAGS (lower 32 bit only) in R11. It then masks RFLAGS with anOS-defined value using the IA32_FMASK (MSR C000_0084). The actual mask valueused by the OS is the complement of the value written to the IA32_FMASK MSR.None of the bits in RFLAGS are automatically cleared (except for RF). SYSRETrestores RFLAGS from R11 (the lower 32 bits only).Software should not alter the CS or SS descriptors in a manner that violates thefollowing assumptions made by SYSCALL/SYSRET:•The CS and SS base and limit remain the same for all processes, including theoperating system (the base is 0H and the limit is 0FFFFFFFFH).••The CS of the SYSCALL target has a privilege level of 0.The CS of the SYSRET target has a privilege level of 3.SYSCALL/SYSRET do not check for violations of these assumptions.OperationIF (CS.L ≠ 1 ) or (IA32_EFER.LMA ≠ 1) or (IA32_EFER.SCE ≠ 1)(* Not in 64-Bit Mode or SYSCALL/SYSRET not enabled in IA32_EFER *)THEN #UD; FI;RCX ← RIP;RIP ← LSTAR_MSR;R11 ← EFLAGS;EFLAGS ← (EFLAGS MASKED BY IA32_FMASK);CPL ← 0;CS(SEL) ← IA32_STAR_MSR[47:32];CS(DPL) ← 0;CS(BASE) ← 0;CS(LIMIT) ← 0xFFFFF;CS(GRANULAR) ← 1;SS(SEL) ← IA32_STAR_MSR[47:32] + 8;SS(DPL) ← 0;SYSCALL—Fast System CallVol.
2B 4-367INSTRUCTION SET REFERENCE, N-ZSS(BASE) ← 0;SS(LIMIT) ← 0xFFFFF;SS(GRANULAR) ← 1;Flags AffectedAll.Protected Mode Exceptions#UDIf Mode≠ 64-bit.Real-Address Mode Exceptions#UDIf Mode≠ 64-bit.Virtual-8086 Mode Exceptions#UDIf Mode≠ 64-bit.Compatibility Mode Exceptions#UDIf Mode≠ 64-bit.64-Bit Mode Exceptions#UDIf IA32_EFER.SCE = 0.If the LOCK prefix is used.4-368 Vol. 2BSYSCALL—Fast System CallINSTRUCTION SET REFERENCE, N-ZSYSENTER—Fast System CallOpcodeInstruction64-BitModeCompat/Leg ModeDescription0F 34SYSENTERValidValidFast call to privilege level 0 systemprocedures.DescriptionExecutes a fast call to a level 0 system procedure or routine.
SYSENTER is acompanion instruction to SYSEXIT. The instruction is optimized to provide themaximum performance for system calls from user code running at privilege level 3 tooperating system or executive procedures running at privilege level 0.Prior to executing the SYSENTER instruction, software must specify the privilegelevel 0 code segment and code entry point, and the privilege level 0 stack segmentand stack pointer by writing values to the following MSRs:•IA32_SYSENTER_CS — Contains a 32-bit value, of which the lower 16 bits arethe segment selector for the privilege level 0 code segment. This value is alsoused to compute the segment selector of the privilege level 0 stack segment.•IA32_SYSENTER_EIP — Contains the 32-bit offset into the privilege level 0 codesegment to the first instruction of the selected operating procedure or routine.•IA32_SYSENTER_ESP — Contains the 32-bit stack pointer for the privilege level0 stack.These MSRs can be read from and written to using RDMSR/WRMSR.
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