Volume 2B Instruction Set Reference N-Z (794102), страница 52
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This instruction is a companion instruction to theSYSENTER instruction.In IA-32e mode, the IA32_SYSENTER_EIP and IA32_SYSENTER_ESP MSRs hold64-bit addresses and must be in canonical form; IA32_SYSENTER_CS must notcontain a NULL selector.When the SYSEXIT instruction transfers control to 64-bit mode user code usingREX.W, the following fields are generated and bits set:•Target code segment — Computed by adding 32 to the value in theIA32_SYSENTER_CS.••••New CS attributes — L-bit = 1 (go to 64-bit mode).Target instruction — Reads 64-bit canonical address in RDX.Stack segment — Computed by adding 8 to the value of CS selector.Stack pointer — Update RSP using 64-bit canonical address in RCX.When SYSEXIT transfers control to compatibility mode user code when the operandsize attribute is 32 bits, the following fields are generated and bits set:•Target code segment — Computed by adding 16 to the value inIA32_SYSENTER_CS.••New CS attributes — L-bit = 0 (go to compatibility mode).Target instruction — Fetch the target instruction from 32-bit address in EDX.SYSEXIT—Fast Return from Fast System CallVol.
2B 4-375INSTRUCTION SET REFERENCE, N-Z••Stack segment — Computed by adding 24 to the value in IA32_SYSENTER_CS.Stack pointer — Update ESP from 32-bit address in ECX.Flags AffectedNone.Protected Mode Exceptions#GP(0)If IA32_SYSENTER_CS[15:2] = 0.If CPL#UD≠ 0.If the LOCK prefix is used.Real-Address Mode Exceptions#GP(0)If protected mode is not enabled.#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)Always.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#GP(0)If IA32_SYSENTER_CS = 0.If CPL≠ 0.If ECX or EDX contains a non-canonical address.#UD4-376 Vol. 2BIf the LOCK prefix is used.SYSEXIT—Fast Return from Fast System CallINSTRUCTION SET REFERENCE, N-ZSYSRET—Return From Fast System CallOpcodeInstruction64-BitModeCompat/Leg ModeDescription0F 07SYSRETValidInvalidReturn from fast system callDescriptionSYSCALL saves the RIP of the instruction following the SYSCALL into RCX and loadsthe new RIP from the LSTAR (64-bit mode only).
Upon return, SYSRET copies thevalue saved in RCX to the RIP.In a return to 64-bit mode using Osize 64, SYSRET sets the CS selector value to MSRIA32_STAR[63:48] +16. The SS is set to IA32_STAR[63:48] + 8.SYSRET transfer control to compatibility mode using Osize 32. The CS selector valueis set to MSR IA32_STAR[63:48]. The SS is set to IA32_STAR[63:48] + 8.It is the responsibility of the OS to keep descriptors in the GDT/LDT that correspondto selectors loaded by SYSCALL/SYSRET consistent with the base, limit and attributevalues forced by the these instructions.Software should not alter the CS or SS descriptors in a manner that violates thefollowing assumptions made by SYSCALL/SYSRET:•CS and SS base and limit remain the same for all processes, including theoperating system.••CS of the SYSCALL target has a privilege level of 0.CS of the SYSRET target has a privilege level of 3.SYSCALL/SYSRET do not check for violations of these assumptions.OperationIF (CS.L ≠ 1 ) or (IA32_EFER.LMA ≠ 1) or (IA32_EFER.SCE ≠ 1)(* Not in 64-Bit Mode or SYSCALL/SYSRET not enabled in IA32_EFER *)THEN #UD; FI;IF (CPL ≠ 0)THEN #GP(0); FI;IF (RCX ≠ CANONICAL_ADDRESS)THEN #GP(0); FI;IF (OPERAND_SIZE = 64)THEN (* Return to 64-Bit Mode *)EFLAGS ← R11;CPL ← 0x3;CS(SEL) ← IA32_STAR[63:48] + 16;CS(PL) ← 0x3;SS(SEL) ← IA32_STAR[63:48] + 8;SYSRET—Return From Fast System CallVol.
2B 4-377INSTRUCTION SET REFERENCE, N-ZSS(PL) ← 0x3;RIP ← RCX;ELSE (* Return to Compatibility Mode *)EFLAGS ← R11;CPL ← 0x3;CS(SEL) ← IA32_STAR[63:48] ;CS(PL) ← 0x3;SS(SEL) ← IA32_STAR[63:48] + 8;SS(PL) ← 0x3;EIP ← ECX;FI;Flags AffectedVM, IF, RF.Protected Mode Exceptions#UDIf Mode≠ 64-Bit.Real-Address Mode Exceptions#UDIf Mode≠ 64-Bit.Virtual-8086 Mode Exceptions#UDIf Mode≠ 64-Bit.Compatibility Mode Exceptions#UDIf Mode≠ 64-Bit.64-Bit Mode Exceptions#UDIf IA32_EFER.SCE bit = 0.If the LOCK prefix is used.#GP(0)If CPL≠ 0.If ECX contains a non-canonical address.4-378 Vol.
2BSYSRET—Return From Fast System CallINSTRUCTION SET REFERENCE, N-ZTEST—Logical CompareOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionA8 ibTEST AL, imm8ValidValidAND imm8 with AL; set SF, ZF,PF according to result.A9 iwTEST AX, imm16ValidValidAND imm16 with AX; set SF,ZF, PF according to result.A9 idTEST EAX, imm32ValidValidAND imm32 with EAX; set SF,ZF, PF according to result.REX.W + A9 idTEST RAX, imm32ValidN.E.AND imm32 sign-extended to64-bits with RAX; set SF, ZF,PF according to result.F6 /0 ibTEST r/m8, imm8ValidValidAND imm8 with r/m8; set SF,ZF, PF according to result.REX + F6 /0 ibTEST r/m8*, imm8ValidN.E.AND imm8 with r/m8; set SF,ZF, PF according to result.F7 /0 iwTEST r/m16,imm16ValidValidAND imm16 with r/m16; setSF, ZF, PF according to result.F7 /0 idTEST r/m32,imm32ValidValidAND imm32 with r/m32; setSF, ZF, PF according to result.REX.W + F7 /0 idTEST r/m64,imm32ValidN.E.AND imm32 sign-extended to64-bits with r/m64; set SF, ZF,PF according to result.84 /rTEST r/m8, r8ValidValidAND r8 with r/m8; set SF, ZF,PF according to result.REX + 84 /rTEST r/m8*, r8*ValidN.E.AND r8 with r/m8; set SF, ZF,PF according to result.85 /rTEST r/m16, r16ValidValidAND r16 with r/m16; set SF,ZF, PF according to result.85 /rTEST r/m32, r32ValidValidAND r32 with r/m32; set SF,ZF, PF according to result.REX.W + 85 /rTEST r/m64, r64ValidN.E.AND r64 with r/m64; set SF,ZF, PF according to result.NOTES:* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix isused: AH, BH, CH, DH.TEST—Logical CompareVol.
2B 4-379INSTRUCTION SET REFERENCE, N-ZDescriptionComputes the bit-wise logical AND of first operand (source 1 operand) and thesecond operand (source 2 operand) and sets the SF, ZF, and PF status flags accordingto the result. The result is then discarded.In 64-bit mode, using a REX prefix in the form of REX.R permits access to additionalregisters (R8-R15).
Using a REX prefix in the form of REX.W promotes operation to64 bits. See the summary chart at the beginning of this section for encoding data andlimits.OperationTEMP ← SRC1 AND SRC2;SF ← MSB(TEMP);IF TEMP = 0THEN ZF ← 1;ELSE ZF ← 0;FI:PF ← BitwiseXNOR(TEMP[0:7]);CF ← 0;OF ← 0;(* AF is undefined *)Flags AffectedThe OF and CF flags are set to 0. The SF, ZF, and PF flags are set according to theresult (see the “Operation” section above). The state of the AF flag is undefined.Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a NULL segmentselector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.4-380 Vol.
2BTEST—Logical CompareINSTRUCTION SET REFERENCE, N-ZReal-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.TEST—Logical CompareVol.
2B 4-381INSTRUCTION SET REFERENCE, N-ZUCOMISD—Unordered Compare Scalar Double-Precision Floating-PointValues and Set EFLAGSOpcodeInstruction64-BitModeCompat/Leg ModeDescription66 0F 2E /rUCOMISD xmm1,xmm2/m64ValidValidCompares (unordered) the low doubleprecision floating-point values inxmm1 and xmm2/m64 and set theEFLAGS accordingly.DescriptionPerforms and unordered compare of the double-precision floating-point values in thelow quadwords of source operand 1 (first operand) and source operand 2 (secondoperand), and sets the ZF, PF, and CF flags in the EFLAGS register according to theresult (unordered, greater than, less than, or equal). The OF, SF and AF flags in theEFLAGS register are set to 0. The unordered result is returned if either sourceoperand is a NaN (QNaN or SNaN).Source operand 1 is an XMM register; source operand 2 can be an XMM register or a64 bit memory location.The UCOMISD instruction differs from the COMISD instruction in that it signals aSIMD floating-point invalid operation exception (#I) only when a source operand isan SNaN.
The COMISD instruction signals an invalid operation exception if a sourceoperand is either a QNaN or an SNaN.The EFLAGS register is not updated if an unmasked SIMD floating-point exception isgenerated.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).OperationRESULT ← UnorderedCompare(SRC1[63:0] < > SRC2[63:0]) {(* Set EFLAGS *)CASE (RESULT) OFUNORDERED:ZF, PF, CF ← 111;GREATER_THAN:ZF, PF, CF ← 000;LESS_THAN:ZF, PF, CF ← 001;EQUAL:ZF, PF, CF ← 100;ESAC;OF, AF, SF ← 0;4-382 Vol.
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