Volume 2B Instruction Set Reference N-Z (794102), страница 55
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2B 4-401INSTRUCTION SET REFERENCE, N-Zor (SegmentDescriptor(Type) ≠ conforming code segment)and (CPL > DPL) or (RPL > DPL)THENZF ← 0;ELSEIF ((Instruction = VERR) and (Segment readable))or ((Instruction = VERW) and (Segment writable))THENZF ← 1;FI;FI;Flags AffectedThe ZF flag is set to 1 if the segment is accessible and readable (VERR) or writable(VERW); otherwise, it is set to 0.Protected Mode ExceptionsThe only exceptions generated for these instructions are those related to illegaladdressing of the source operand.#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register is used to access memory and itcontains a NULL segment selector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#UDThe VERR and VERW instructions are not recognized in realaddress mode.If the LOCK prefix is used.Virtual-8086 Mode Exceptions#UDThe VERR and VERW instructions are not recognized in virtual8086 mode.If the LOCK prefix is used.4-402 Vol.
2BVERR/VERW—Verify a Segment for Reading or WritingINSTRUCTION SET REFERENCE, N-ZCompatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.VERR/VERW—Verify a Segment for Reading or WritingVol. 2B 4-403INSTRUCTION SET REFERENCE, N-ZWAIT/FWAIT—WaitOpcodeInstruction64-Bit Mode Compat/Leg ModeDescription9BWAITValidValidCheck pending unmasked floatingpoint exceptions.9BFWAITValidValidCheck pending unmasked floatingpoint exceptions.DescriptionCauses the processor to check for and handle pending, unmasked, floating-pointexceptions before proceeding.
(FWAIT is an alternate mnemonic for WAIT.)This instruction is useful for synchronizing exceptions in critical sections of code.Coding a WAIT instruction after a floating-point instruction insures that anyunmasked floating-point exceptions the instruction may raise are handled before theprocessor can modify the instruction’s results. See the section titled “Floating-PointException Synchronization” in Chapter 8 of the Intel® 64 and IA-32 ArchitecturesSoftware Developer’s Manual, Volume 1, for more information on using theWAIT/FWAIT instruction.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.OperationCheckForPendingUnmaskedFloatingPointExceptions;FPU Flags AffectedThe C0, C1, C2, and C3 flags are undefined.Floating-Point ExceptionsNone.Protected Mode Exceptions#NMIf CR0.MP[bit 1] = 1 and CR0.TS[bit 3] = 1.#UDIf the LOCK prefix is used.Real-Address Mode ExceptionsSame exceptions as in protected mode.Virtual-8086 Mode ExceptionsSame exceptions as in protected mode.4-404 Vol.
2BWAIT/FWAIT—WaitINSTRUCTION SET REFERENCE, N-ZCompatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode ExceptionsSame exceptions as in protected mode.WAIT/FWAIT—WaitVol. 2B 4-405INSTRUCTION SET REFERENCE, N-ZWBINVD—Write Back and Invalidate CacheOpcodeInstruction64-BitModeCompat/Leg ModeDescription0F 09WBINVDValidValidWrite back and flush Internal caches;initiate writing-back and flushing ofexternal caches.DescriptionWrites back all modified cache lines in the processor’s internal cache to main memoryand invalidates (flushes) the internal caches.
The instruction then issues a specialfunction bus cycle that directs external caches to also write back modified data andanother bus cycle to indicate that the external caches should be invalidated.After executing this instruction, the processor does not wait for the external cachesto complete their write-back and flushing operations before proceeding with instruction execution.
It is the responsibility of hardware to respond to the cache write-backand flush signals.The WBINVD instruction is a privileged instruction. When the processor is running inprotected mode, the CPL of a program or procedure must be 0 to execute thisinstruction. This instruction is also a serializing instruction (see “Serializing Instructions” in Chapter 8 of the Intel® 64 and IA-32 Architectures Software Developer’sManual, Volume 3A).In situations where cache coherency with main memory is not a concern, softwarecan use the INVD instruction.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.IA-32 Architecture CompatibilityThe WBINVD instruction is implementation dependent, and its function may beimplemented differently on future Intel 64 and IA-32 processors. The instruction isnot supported on IA-32 processors earlier than the Intel486 processor.OperationWriteBack(InternalCaches);Flush(InternalCaches);SignalWriteBack(ExternalCaches);SignalFlush(ExternalCaches);Continue; (* Continue execution *)Flags AffectedNone.4-406 Vol.
2BWBINVD—Write Back and Invalidate CacheINSTRUCTION SET REFERENCE, N-ZProtected Mode Exceptions#GP(0)If the current privilege level is not 0.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)WBINVD cannot be executed at the virtual-8086 mode.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode ExceptionsSame exceptions as in protected mode.WBINVD—Write Back and Invalidate CacheVol.
2B 4-407INSTRUCTION SET REFERENCE, N-ZWRMSR—Write to Model Specific RegisterOpcodeInstruction64-BitModeCompat/Leg ModeDescription0F 30WRMSRValidValidWrite the value in EDX:EAX to MSRspecified by ECX.DescriptionWrites the contents of registers EDX:EAX into the 64-bit model specific register(MSR) specified in the ECX register.
(On processors that support the Intel 64 architecture, the high-order 32 bits of RCX are ignored.) The contents of the EDX registerare copied to high-order 32 bits of the selected MSR and the contents of the EAXregister are copied to low-order 32 bits of the MSR. (On processors that support theIntel 64 architecture, the high-order 32 bits of each of RAX and RDX are ignored.)Undefined or reserved bits in an MSR should be set to values previously read.This instruction must be executed at privilege level 0 or in real-address mode; otherwise, a general protection exception #GP(0) is generated.
Specifying a reserved orunimplemented MSR address in ECX will also cause a general protection exception.The processor will also generate a general protection exception if software attemptsto write to bits in a reserved MSR.When the WRMSR instruction is used to write to an MTRR, the TLBs are invalidated.This includes global entries (see “Translation Lookaside Buffers (TLBs)” in Chapter 3of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A).MSRs control functions for testability, execution tracing, performance-monitoringand machine check errors.
Appendix B, “Model-Specific Registers (MSRs)”, in theIntel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B, lists allMSRs that can be read with this instruction and their addresses. Note that eachprocessor family has its own set of MSRs.The WRMSR instruction is a serializing instruction (see “Serializing Instructions” inChapter 7 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual,Volume 3A).The CPUID instruction should be used to determine whether MSRs are supported(CPUID.01H:EDX[5] = 1) before using this instruction.IA-32 Architecture CompatibilityThe MSRs and the ability to read them with the WRMSR instruction were introducedinto the IA-32 architecture with the Pentium processor.
Execution of this instructionby an IA-32 processor earlier than the Pentium processor results in an invalid opcodeexception #UD.4-408 Vol. 2BWRMSR—Write to Model Specific RegisterINSTRUCTION SET REFERENCE, N-ZOperationMSR[ECX] ← EDX:EAX;Flags AffectedNone.Protected Mode Exceptions#GP(0)If the current privilege level is not 0.If the value in ECX specifies a reserved or unimplemented MSRaddress.If the value in EDX:EAX sets bits that are reserved in the MSRspecified by ECX.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#GP(0)If the value in ECX specifies a reserved or unimplemented MSRaddress.If the value in EDX:EAX sets bits that are reserved in the MSRspecified by ECX.#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)The WRMSR instruction is not recognized in virtual-8086 mode.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode ExceptionsSame exceptions as in protected mode.WRMSR—Write to Model Specific RegisterVol.
2B 4-409INSTRUCTION SET REFERENCE, N-ZXADD—Exchange and AddOpcodeInstruction64-Bit Mode Compat/Leg ModeDescription0F C0 /rXADD r/m8, r8ValidValidExchange r8 and r/m8; loadsum into r/m8.REX + 0F C0 /rXADD r/m8*, r8*ValidN.E.Exchange r8 and r/m8; loadsum into r/m8.0F C1 /rXADD r/m16, r16ValidValidExchange r16 and r/m16;load sum into r/m16.0F C1 /rXADD r/m32, r32ValidValidExchange r32 and r/m32;load sum into r/m32.REX.W + 0F C1 /rXADD r/m64, r64ValidN.E.Exchange r64 and r/m64;load sum into r/m64.NOTES:* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix isused: AH, BH, CH, DH.DescriptionExchanges the first operand (destination operand) with the second operand (sourceoperand), then loads the sum of the two values into the destination operand.
Thedestination operand can be a register or a memory location; the source operand is aregister.In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefixin the form of REX.R permits access to additional registers (R8-R15). Using a REXprefix in the form of REX.W promotes operation to 64 bits.
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