Volume 2B Instruction Set Reference N-Z (794102), страница 57
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See the summary chart at the beginning ofthis section for encoding data and limits.OperationIF AddressSize = 16THENAL ← (DS:BX + ZeroExtend(AL));ELSE IF (AddressSize = 32)AL ← (DS:EBX + ZeroExtend(AL)); FI;ELSE (AddressSize = 64)4-416 Vol. 2BXLAT/XLATB—Table Look-up TranslationINSTRUCTION SET REFERENCE, N-ZAL ← (RBX + ZeroExtend(AL));FI;Flags AffectedNone.Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a NULL segmentselector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)If a page fault occurs.#UDIf the LOCK prefix is used.XLAT/XLATB—Table Look-up TranslationVol.
2B 4-417INSTRUCTION SET REFERENCE, N-ZXOR—Logical Exclusive OROpcodeInstruction64-BitModeCompat/Leg ModeDescription34 ibXOR AL, imm8ValidValidAL XOR imm8.35 iwXOR AX, imm16ValidValidAX XOR imm16.35 idXOR EAX, imm32ValidValidEAX XOR imm32.REX.W + 35 idXOR RAX, imm32ValidN.E.RAX XOR imm32 (signextended).80 /6 ibXOR r/m8, imm8ValidValidr/m8 XOR imm8.REX + 80 /6 ibXOR r/m8*, imm8ValidN.E.r/m8 XOR imm8.81 /6 iwXOR r/m16, imm16ValidValidr/m16 XOR imm16.81 /6 idXOR r/m32, imm32ValidValidr/m32 XOR imm32.REX.W + 81 /6 idXOR r/m64, imm32ValidN.E.r/m64 XOR imm32 (signextended).83 /6 ibXOR r/m16, imm8ValidValidr/m16 XOR imm8 (signextended).83 /6 ibXOR r/m32, imm8ValidValidr/m32 XOR imm8 (signextended).REX.W + 83 /6 ibXOR r/m64, imm8ValidN.E.r/m64 XOR imm8 (signextended).30 /rXOR r/m8, r8ValidValidr/m8 XOR r8.REX + 30 /rXOR r/m8*, r8*ValidN.E.r/m8 XOR r8.31 /rXOR r/m16, r16ValidValidr/m16 XOR r16.31 /rXOR r/m32, r32ValidValidr/m32 XOR r32.REX.W + 31 /rXOR r/m64, r64ValidN.E.r/m64 XOR r64.32 /rXOR r8, r/m8ValidValidr8 XOR r/m8.REX + 32 /rXOR r8*, r/m8*ValidN.E.r8 XOR r/m8.33 /rXOR r16, r/m16ValidValidr16 XOR r/m16.33 /rXOR r32, r/m32ValidValidr32 XOR r/m32.REX.W + 33 /rXOR r64, r/m64ValidN.E.r64 XOR r/m64.NOTES:* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix isused: AH, BH, CH, DH.4-418 Vol.
2BXOR—Logical Exclusive ORINSTRUCTION SET REFERENCE, N-ZDescriptionPerforms a bitwise exclusive OR (XOR) operation on the destination (first) and source(second) operands and stores the result in the destination operand location. Thesource operand can be an immediate, a register, or a memory location; the destination operand can be a register or a memory location. (However, two memory operands cannot be used in one instruction.) Each bit of the result is 1 if thecorresponding bits of the operands are different; each bit is 0 if the correspondingbits are the same.This instruction can be used with a LOCK prefix to allow the instruction to beexecuted atomically.In 64-bit mode, using a REX prefix in the form of REX.R permits access to additionalregisters (R8-R15).
Using a REX prefix in the form of REX.W promotes operation to64 bits. See the summary chart at the beginning of this section for encoding data andlimits.OperationDEST ← DEST XOR SRC;Flags AffectedThe OF and CF flags are cleared; the SF, ZF, and PF flags are set according to theresult. The state of the AF flag is undefined.Protected Mode Exceptions#GP(0)If the destination operand points to a non-writable segment.If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a NULL segmentselector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.XOR—Logical Exclusive ORVol.
2B 4-419INSTRUCTION SET REFERENCE, N-Z#UDIf the LOCK prefix is used but the destination is not a memoryoperand.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.4-420 Vol.
2BXOR—Logical Exclusive ORINSTRUCTION SET REFERENCE, N-ZXORPD—Bitwise Logical XOR for Double-Precision Floating-PointValuesOpcodeInstruction64-BitModeCompat/Leg ModeDescription66 0F 57 /rXORPD xmm1, xmm2/m128ValidValidBitwise exclusive-OR ofxmm2/m128 and xmm1.DescriptionPerforms a bitwise logical exclusive-OR of the two packed double-precision floatingpoint values from the source operand (second operand) and the destination operand(first operand), and stores the result in the destination operand. The source operandcan be an XMM register or a 128-bit memory location. The destination operand is anXMM register.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).OperationDEST[127:0] ← DEST[127:0] BitwiseXOR SRC[127:0];Intel C/C++ Compiler Intrinsic EquivalentXORPD__m128d _mm_xor_pd(__m128d a, __m128d b)SIMD Floating-Point ExceptionsNone.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.XORPD—Bitwise Logical XOR for Double-Precision Floating-Point ValuesVol.
2B 4-421INSTRUCTION SET REFERENCE, N-ZReal-Address Mode Exceptions#GP(0)If a memory operand is not aligned on a 16-byte boundary,regardless of segment.If any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)#GP(0)If a memory address referencing the SS segment is in a noncanonical form.If the memory address is in a non-canonical form.If memory operand is not aligned on a 16-byte boundary,regardless of segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.4-422 Vol.
2BXORPD—Bitwise Logical XOR for Double-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, N-ZXORPS—Bitwise Logical XOR for Single-Precision Floating-Point Values64-BitModeOpcodeInstruction0F 57 /rXORPS xmm1, xmm2/m128 ValidCompat/Leg ModeValidDescriptionBitwise exclusive-OR ofxmm2/m128 and xmm1.DescriptionPerforms a bitwise logical exclusive-OR of the four packed single-precision floatingpoint values from the source operand (second operand) and the destination operand(first operand), and stores the result in the destination operand.
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